参数资料
型号: ADT7462ZEVB
厂商: ON Semiconductor
文件页数: 54/82页
文件大小: 0K
描述: BOARD EVALUATION FOR ADT7462
产品变化通告: MFG CHG Notification ADI to ON Semi
标准包装: 1
类型: 温度传感器
适用于相关产品: ADT7462
所含物品: 评估板
其它名称: EVAL-ADT7462EBZ
EVAL-ADT7462EBZ-ND
ADT7462
Switching on the V CCP1 rail gates the fan’s quiet
startup counter.
3. V BATT is monitored immediately on powerup
before the setup complete bit (Register 0x01,
Bit 5) is set. The chassis intrusion circuit (CI) is
powered from V BATT . If the measured V BATT
reading is lower than the lower limit
(default = 0x80), the CI circuit is turned off.
4. PWM1, PWM2, and PWM4 are not on dedicated
pins. Because these pins are shared with inputs,
they are allowed to float high on powerup. This
means that if a fan is connected to these pins, it
spins at full speed on powerup.
5. PWM3 is switched off by default (because this is a
dedicated pin). If no SMBus communication takes
place within 4.6 seconds of the V CCP rail
switching on, this PWM drive is driven to full
speed. If SMBus communication does take place,
this pin behaves as programmed.
6. No temperature or voltage (other than V CCP1 ,
Diode 2, and V BATT ) is monitored until the setup
complete bit (Bit 5) is set in Configuration
Register 1 (0x01). This allows the user to program
the ADT7462 as required before monitoring of all
channel s is enabled, thereby not generating false
ALERTs. The setup complete bit should not be set
PIN 1
PIN 2
PIN 3
PIN 4
PIN 7
PIN 8
PIN 16
PIN 20
until the device is fully configured for the desired
monitoring functions.
The following steps describe how to set up the ADT7462:
1. Powerup the device.
2. Choose the best-suited easy configuration option
for the application, changing pin functions as
required.
3. Program all appropriate limits for monitored
inputs. Program device parameters, fan control
parameters, mask bits, and anything else required
for the application.
4. Set the setup complete bit. Do not set this bit until
the device is fully set up.
XOR Tree Test
The ADT7462 includes an XOR tree test mode. This
mode is useful for in-circuit test equipment at board-level
testing. By applying stimulus to the pins included in the
XOR test, it is possible to detect opens or shorts on the
system board. Figure 86 shows the signals exercised in the
XOR tree test. The XOR tree test is invoked by setting Bit 6
(XOR) of Configuration Register 3 (0x03).
Note that the digital inputs must be selected on
multifunctional pins for the XOR tree test mode. Pin 13 is
the open-drain output of the XOR tree test.
PIN 25
PIN 26
PIN 27
PIN 28
PIN 29
PIN 31
PIN 13
PIN 32
PIN 21
PIN 22
Figure 86. XOR Tree Test
http://onsemi.com
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