参数资料
型号: ADUC7032BSTZ-88-RL
厂商: Analog Devices Inc
文件页数: 4/120页
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
标准包装: 2,000
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 1.5K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 带卷 (TR)
ADuC7032-8L
Rev. A | Page 101 of 120
SERIAL PERIPHERAL INTERFACE
The ADuC7032-8L features a complete hardware serial
peripheral interface (SPI) on-chip. SPI is an industry-standard
synchronous serial interface that allows eight bits of data to be
synchronously transmitted and received simultaneously, that is,
full duplex.
The SPI is operational only with core clock divider bits
(POWCON[2:0] = 0 or 1).
The SPI port can be configured for master or slave operation
and consists of four pins that are multiplexed with four GPIOs.
The four SPI pins are MISO, MOSI, SCLK, and SS. The pins to
which these signals are connected are shown in
.
Table 87. SPI Output Pins
Pin
Signal
Description
GPIO_0 (GPIO MODE 1)
SS
Chip Select
GPIO_1 (GPIO MODE 1)
SCLK
Serial Clock
GPIO_2 (GPIO MODE 1)
MISO
Master In, Slave Out
GPIO_3 (GPIO MODE 1)
MOSI
Master Out, Slave In
MISO (MASTER IN, SLAVE OUT DATA I/O PIN)
The MISO (master in, slave out) pin is configured as an input
line in master mode and an output line in slave mode. The
MISO line on the master (data in) should be connected to the
MISO line in the slave device (data out). The data is transferred
as byte wide (8-bit) serial data, MSB first.
MOSI (MASTER OUT, SLAVE IN PIN)
The MOSI (master out, slave in) pin is configured as an output
line in master mode and an input line in slave mode. The MOSI
line on the master (data out) should be connected to the MOSI
line in the slave device (data in). The data is transferred as byte
wide (8-bit) serial data, MSB first.
SCLK (SERIAL CLOCK I/O PIN)
The master serial clock (SCLK) is used to synchronize the data
being transmitted and received through the MOSI SCLK period.
Therefore, a byte is transmitted/received after eight SCLK
periods. The SCLK pin is configured as an output in master
mode and as an input in slave mode.
In master mode, polarity and phase of the clock are controlled
by the SPICON register, and the bit rate is defined in the
SPIDIV register as follows:
)
1
(
2
MHz
48
.
20
SPIDIV
f
K
SERIALCLOC
+
×
=
The maximum speed of the SPI clock is dependent on the clock
divider bits and is summarized in Table 88.
Table 88. SPI Speed vs. Clock Divider Bits in Master Mode
CD Bits
0
1
SPIDIV
0x05
0x0B
Maximum SCLK
1.667 MHz
0.833 MHz
In slave mode, the SPICON register must be configured with
the phase and polarity of the expected input clock. The slave
accepts data from an external master up to 5.12 Mb at CD = 0.
The formula to determine the maximum speed follows:
4
HCLK
K
SERIALCLOC
f
=
In both master and slave modes, data is transmitted on one edge
of the SCL signal and sampled on the other. Therefore, it is impor-
tant that the polarity and phase be configured in the same way
for the master and slave devices.
CHIP SELECT (SS) INPUT PIN
In SPI slave mode, a transfer is initiated by the assertion of SS,
which is an active low input signal. The SPI port then transmits
and receives 8-bit data until the transfer is concluded by
deassertion of SS. In slave mode, SS is always an input.
SPI REGISTERS DEFINITIONS
The following MMR registers are used to control the SPI interface:
SPICON: 16-bit control register
SPISTA: 8-bit read-only status register
SPIDIV: 8-bit serial clock divider register
SPIRX: 8-bit read-only receive register
SPITX: 8-bit write-only transmit register
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