参数资料
型号: ADUC7032BSTZ-88-RL
厂商: Analog Devices Inc
文件页数: 87/120页
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
标准包装: 2,000
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 1.5K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 带卷 (TR)
ADuC7032-8L
Rev. A | Page 69 of 120
TIMERS
The ADuC7032-8L features four general-purpose
timers/counters.
Timer0, or lifetime timer
Timer1
Timer2 or wake-up timer
Timer3 or watchdog timer
The four timers in their normal mode of operation can be in
either free running mode or periodic mode.
Timers are started by writing data to the control register of the
corresponding timer (TxCON). The counting mode and speed
depend on the configuration chosen in TxCON.
In normal mode, an IRQ is generated each time the value of
the counter reaches 0 when counting down, or each time the
counter value reaches full scale when counting up. An IRQ
can be cleared by writing any value to clear the register of
that particular timer (TxCLRI).
The three timers in their normal mode of operation can be
either free-running or periodic.
In free-running mode, starting with the value in the TxLD
register, the counter decrements/increments from the maximum/
minimum value until zero/full scale and starts again at the
maximum/minimum value. This means that, in free-running
mode, TxVAL is not reloaded when the relevant interrupt bit is
set but the count simply rolls over as the counter underflows or
overflows.
In periodic mode, the counter decrements/increments from
the value in the load register (TxLD MMR) until zero/full scale
starts again from this value. This means when the relevant
interrupt bit is set, TxVAL is reloaded with TxLD and counting
starts again from this value.
Loading the TxLD register with zero is not recommended. The
value of a counter can be read at any time by accessing its value
register (TxVAL).
In addition, Timer0 and Timer1 each has a capture register
(T0CAP and T1CAP, respectively) that can hold the value
captured by an enabled IRQ event. The IRQ events are
described in Table 53.
Table 53. Timer Event Capture
Bit
Description
Comments
0
Timer0.
See the Timer0—Lifetime Timer section.
1
Timer1.
See the Timer1 section.
2
Timer2 or Wake-Up Timer.
See the Timer2—Wake-Up Timer section.
3
Timer3 or Watchdog Timer.
See the Timer3—Watchdog Timer section.
4
Reserved.
Should be written as 0.
5
LIN Hardware.
6
Flash/EE Interrupt.
7
PLL Lock.
8
ADC.
9
UART.
See the UART Serial Interface section.
10
SPI Master.
11
XIRQ0 (GPIO IRQ 0).
See the General-Purpose I/O section.
12
XIRQ1 (GPIO IRQ 1).
See the General-Purpose I/O section.
13
Reserved.
Should be written as 0.
14
IRQ3 High Voltage IRQ.
15
SPI Slave.
16
XIRQ4 (GPIO IRQ 4).
See the General-Purpose I/O section.
17
XIRQ5 (GPIO IRQ 5).
See the General-Purpose I/O section.
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