参数资料
型号: ADUC7032BSTZ-88-RL
厂商: Analog Devices Inc
文件页数: 49/120页
文件大小: 0K
描述: IC MCU 96K FLASH DUAL 48LQFP
标准包装: 2,000
系列: MicroConverter® ADuC7xxx
核心处理器: ARM7
芯体尺寸: 16/32-位
速度: 20.48MHz
连通性: LIN,SPI,UART/USART
外围设备: POR,PSM,温度传感器,WDT
输入/输出数: 9
程序存储器容量: 96KB(48K x 16)
程序存储器类型: 闪存
RAM 容量: 1.5K x 32
电压 - 电源 (Vcc/Vdd): 3.5 V ~ 18 V
数据转换器: A/D 2x16b
振荡器型: 内部
工作温度: -40°C ~ 105°C
封装/外壳: 48-LQFP
包装: 带卷 (TR)
ADuC7032-8L
Rev. A | Page 34 of 120
MEMORY MAPPED REGISTERS
The memory mapped register (MMR) space is mapped into the
top 4 kB of the MCU memory space and accessed by indirect
addressing, load, and store commands through the ARM7
banked registers. An outline of the memory mapped register
bank of the ADuC7032-8L is shown in Figure 14.
The MMR space provides an interface between the CPU and all
on-chip peripherals. All registers except the ARM7 core registers
(described in the ARM Registers section) reside in the MMR area.
As seen in the Complete MMR Listing section (Table 20 to
Table 30), the MMR data widths vary from one byte (eight bits)
to four bytes (32 bits). The ARM7 core can access any of the
MMRs (single-byte or multiple-byte width registers) with
a 32-bit read or write access.
The resultant read, for example, is aligned per the little endian
format described in the Memory Format section. However,
errors result if the ARM7 core tries to access 4-byte (32-bit)
MMRs with a 16-bit access. In the case of a (16-bit) write access
to a 32-bit MMR, the (upper) 16 most significant bits are
written as 0s. More obviously, in the case of a 16-bit read access
to a 32-bit MMR, only 16 of the MMR bits can be read.
FLASH CONTROL
INTERFACE
GPIO
SPI
HV INTERFACE
LIN
HARDWARE
UART
ADC
PLL AND
OSCILLATOR CONTROL
WATCHDOG
TIMER3
WAKE-UP
TIMER2
GENERAL-PURPOSE
TIMER1
TIMER0
REMAP AND
SYSTEM CONTROL
INTERRUPT
CONTROLLER
0xFFFFFFFF
0xFFFF1000
0xFFFF0E00
0xFFFF0D50
0xFFFF0D00
0xFFFF0A14
0xFFFF0A00
0xFFFF0810
0xFFFF0800
0xFFFF079C
0xFFFF0780
0xFFFF0730
0xFFFF0700
0xFFFF0568
0xFFFF0500
0xFFFF044C
0xFFFF0400
0xFFFF0370
0xFFFF0360
0xFFFF0350
0xFFFF0340
0xFFFF0334
0xFFFF0320
0xFFFF0318
0xFFFF0300
0xFFFF0244
0xFFFF0220
0xFFFF0110
0xFFFF0000
05
98
6-
01
4
Figure 14. Top Level MMR Map
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