参数资料
型号: ADUC832BCPZ
厂商: Analog Devices Inc
文件页数: 60/92页
文件大小: 0K
描述: IC MCU 62K FLASH ADC/DAC 56LFCSP
标准包装: 1
系列: MicroConverter® ADuC8xx
核心处理器: 8052
芯体尺寸: 8-位
速度: 16MHz
连通性: EBI/EMI,I²C,SPI,UART/USART
外围设备: PSM,温度传感器,WDT
输入/输出数: 34
程序存储器容量: 62KB(62K x 8)
程序存储器类型: 闪存
EEPROM 大小: 4K x 8
RAM 容量: 2.25K x 8
电压 - 电源 (Vcc/Vdd): 2.7 V ~ 5.5 V
数据转换器: A/D 8x12b,D/A 2x12b
振荡器型: 内部
工作温度: -40°C ~ 85°C
封装/外壳: 56-VFQFN 裸露焊盘,CSP
包装: 托盘
Data Sheet
ADuC832
Rev. B | Page 63 of 92
POWER SUPPLY MONITOR
As its name suggests, the power supply monitor, once enabled,
monitors the DVDD supply on the ADuC832. It indicates when
any of the supply pins drop below one of four user-selectable
voltage trip points from 2.63 V to 4.37 V. For correct operation
of the power supply monitor function, AVDD must be equal to
or greater than 2.7 V. The monitor function is controlled via
the PSMCON SFR. If enabled via the IEIP2 SFR, the monitor
interrupts the core using the PSMI bit in the PSMCON SFR.
This bit is not cleared until the failing power supply has returned
above the trip point for at least 250 ms. This monitor function
allows the user to save working registers to avoid possible data
loss due to the low supply condition, and ensures that normal
code execution does not resume until a safe supply level has
been well established. The supply monitor is also protected
against spurious glitches triggering the interrupt circuit.
PSMCON (POWER SUPPLY MONITOR CONTROL
REGISTER )
SFR Address:
DFH
Power-On Default Value:
DEH
Bit Addressable :
No
Table 31. PSMCON SFR Bit Designations
Bit
Name
Description
[7]
Reserved
Reserved.
[6]
CMPD
DVDD comparator bit.
This is a read-only bit and directly reflects the state of the DVDD comparator.
Read 1 indicates the DVDD supply is above its selected trip point.
Read 0 indicates the DVDD supply is below its selected trip point.
[5]
PSMI
Power supply monitor interrupt bit.
This bit is set high by the MicroConverter if CMPD is low, indicating low analog or digital supply. The PSMI bit can be
used to interrupt the processor. Once CMPD returns (and remains) high, a 250 ms counter is started. When this counter
times out, the PSMI interrupt is cleared. PSMI can also be written by the user. However, if either comparator output is
low, it is not possible for the user to clear PSMI.
[4:3]
TPD[1:0]
DVDD trip point selection bits. These bits select the DVDD trip point voltage as follows:
TPD1
TPD0
Selected DVDD Trip Point (V)
0
4.37
0
1
3.08
1
0
2.93
1
2.63
[2]
Reserved
Reserved.
[1]
Reserved
Reserved.
[0]
PSMEN
Power supply monitor enable bit. Set to 1 by the user to enable the power supply monitor circuit. Cleared to 0 by the
user to disable the power supply monitor circuit.
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