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| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 16/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Alert on LAN* ASIC — Networking Silicon
12
Datasheet
2.9
Miscellaneous Logic
The Alert on LAN ASIC has a block of miscellaneous logic, consisting of registers, reset circuitry,
and PWR_GOOD monitoring. The power monitoring is significant and explained in this section.
The Alert on LAN ASIC monitors two input signals, PWR_GOOD and AUX_GOOD, to indicate
the status of the main power supply and the auxiliary power supply, respectively. These signals
allow the Alert on LAN ASIC to determine the state of the power supplies and control the 82558B
appropriately. This enables the Alert on LAN ASIC to determine whether or not the PCI interface
is active.
In order to guarantee that ALTRST# is asserted before ISOLATE#, the Alert on LAN ASIC
provides the combinational logic driven by PWR_GOOD and AUX_GOOD to control the
ISOLATE# output. This is important since the 82558B will not be able to propagate a reset unless
four clock cycles are present while ALTRST# or PCI_RST# is active and ISOLATE# is inactive.
Another main function of the Alert on LAN ASIC is to determine when power has been lost or
attained to the main power plane. This allows the Alert on LAN ASIC to enable or disable certain
events as necessary for the different power states.
The Alert on LAN ASIC monitors the Main Power Good signal at all times and is designed to
detect when the system has been powered down with or without software knowledge. When the
system is powered down normally, software will set the ACPI state in the ACPI State Indicator bits
of the Control register to ACPI G2 state (10b), anticipating a power-down. From this state, the
Alert on LAN ASIC will continue operating normally if the system is powered down (for example,
the Main Power Good signal transitions from high to low). However, if the ACPI system state is not
set to G2 when the Main Power Good signal transitions from high to low, the Alert on LAN ASIC
will force a re-read of the EEPROM to load its default values. This ensures that the Alert on LAN
ASIC will be able to operate in a known state, rather than an unpredictable state due to the software
unaware power-down.
PCI_RST# is used as an input to the Alert on LAN ASIC and as a stimulus to reset the 82558B
with the 82558_RST# signal. In a system with the Alert on LAN management solution, it is
undesirable to reset the 82558B while the Main Power Good signal is low. The Alert on LAN ASIC
only allows PCI_RST# to assert 82558_RST# when the Main Power Good signal is 1b. This input
can also cause the Alert on LAN ASIC to terminate any TCO transactions with the 82558B until it
can continue at a later time. The Alert on LAN ASIC offers software the capability of resetting the
82558B through the use of the CTL_558RST bit in the Control register (
Section 4.11, “Register 9h;
Control” on page 22
).
The Main Power Good signal effect on the propagation of PCI_RST# to 82558_RST# is important
since PIIX4 will assert a PCI_RST# when power is being lost. However, PCI_RST# will reset the
82558B which is undesirable. Therefore, the Alert on LAN ASIC uses the Main Power Good signal
to determine if PCI_RST# should be propagated or not. This assumes that the Main Power Good
signal is de-asserted before PCI_RST#.
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