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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 9/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
5
Networking Silicon — Alert on LAN* ASIC
2.2
SMB Interface
The SMB interface is a slave-only interface. Since the Alert on LAN ASIC is completely under
software control and provides interrupts via the SMI output signal (SMI#), an SMB alert signal is
not supported.
The SMB address the ASIC responds to is determined at reset time. After an EEPROM load has
completed (due to hardware or software reset or the Main Power Good signal transition to low),
TDATA[2:0] are internally latched and are inputs during an EEPROM load and reset. The
TDATA[2:0] lines are multiplexed with the SMB address lines 2 through 0 (SMB_A[2:0]). The
value of these input pins, SMB_A[2:0], are used to create the SMB address of 0101XXXb, where
XXX represents SMB_A2, SMB_A1, and SMB_A0, respectively. These inputs can be configured
using pull-up or pull-down resistors. There are default pull-up and pull-down resistors in the silicon
to select 110b on SMB_A[2:0]. However, the internal pull-up resistors in the device for the SMB
address are too weak; therefore, all ones for SMB address lines require a strong, external pull-up
resistor (for example, a value of 2 K
). Resistor values and tolerances are described in
Section 6.0,
“Electrical Specifications” on page 27
.
More details on SMB can be found in the
Intel System Management Bus Specification, Revision
1.0
.
For register accesses to the Alert on LAN ASIC, a simple set of SMB commands are supported:
Write Byte command and Read Byte command. The command field can be used to access the
individual registers.
Explicit details on the SMB cycles and bit definitions are described in
Section 4.0, “Configuration
and Status Registers” on page 17
.
The SMB interface can be configured to drive the SMB Data Input/Output and SMB Serial Clock
pins low when the Main Power Good signal equals 0b by using the Drive SMB bit of the Control
register. This is one method of preventing the open drain bus from floating when other SMB
connections have been powered-off. After reset, the SMB interface will be driven low if the Main
Power Good signal equals 0b until the Control register is read. At this point, the function will
depend on the configuration bit. It requires approximately 125 microseconds from reset to read the
Drive SMB bit in the Control register.
2.3
EEPROM Interface
Note:
The Alert on LAN ASIC requires a 64x16 EEPROM which is separate from the 82558B's
EEPROM.
The EEPROM interface is provided to allow default configuration information. This gives the Alert
on LAN ASIC a default power-up state of enabled and disabled events, IP packet information,
Individual Address, and other configuration data.
The Alert on LAN ASIC reads information from the EEPROM during the following:
Hardware Reset
. This happens when the Alert on LAN ASIC is first powered-up or when the
Auxiliary Power Good (AUX_GOOD) signal transitions low. The Alert on LAN ASIC begins
loading the EEPROM configuration information as soon as reset is de-asserted.
Software Reset
. This is accomplished by writing to bit 7 of the Test Mode register via the
SMB. After reset has completed, the Alert on LAN ASIC begins reading the EEPROM.
Hard Transition to G2 Power State
. A hard transition to the G2 power state occurs when the
system is powered down before software notifies the Alert on LAN ASIC of the transition by
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