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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 22/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Alert on LAN* ASIC — Networking Silicon
18
Datasheet
is cleared by writing a 1b to bit 0 and the Clear Sticky Latch Polarity bit (POL_CLREV1) in the
Event Polarity register equals 1b, the EVENT_1 pin outputs the opposite of the Event Polarity
register bit between 20 and 40 milliseconds.
4.4
Register 2h; Event Polarity
The Event Polarity register is used to set the polarity of the event inputs. This flexibility allows the
Alert on LAN to handle external interfaces that are either active low or active high.
Bits
Name
Type
Name and Description
Default
7
STA_SWE
R/W
SC
Software Event Status.
This bit is set if software
causes an event. It can also be forced by writing a 1b to
this bit.
1 = Force Software Event
This bit self-clears after three software event packet
transmissions.
0b
6
STA_WDG
R/W1
Watchdog Event Status.
This bit is set if the
Watchdog Timer has expired. Writing a 1b to this bit
clears it.
1 = Watchdog Timer expired
0b
5
Reserved
This bit is reserved and should be set to 0b.
0b
4
STA_EV5
R/W1
Event_5 Status.
This bit indicates status of Event 5,
Processor Missing. It is set if the processor is not
installed. Writing a 1b to this bit clears it.
1 = Event_5 occurred
0b
3
STA_EV4
R/W1
Event_4 Status.
This bit indicates status of Event 4,
LAN Leash. It is set if the LAN has lost its link. Writing a
1b to this bit clears it.
1 = Event_4 occurred
1b
a
2
STA_EV3
R/W1
Event_3 Status.
This bit indicates status of Event 3,
BTI Temperature. It is set if the BTI temperature is out
of the specified range. Writing a 1b to this bit clears it.
1 = Event_3 occurred
0b
1
STA_EV2
R/W1
Event_2 Status.
This bit indicates status of Event 2,
ENV_SMI. It is set if the hardware monitoring device
has an SMI event. Writing a 1b to this bit clears it.
1 = Event_2 occurred
0b
0
STA_EV1
R/W1
Event_1 Status.
This bit indicates status of Event 1,
Cover Tamper. It is set if the cover has been opened or
tampered with. Writing a 1 to this bit clears it.
1 = Event_1 occurred
0b
a. A hardware reset causes this bit to return to its default value of 1b; a software reset leaves this bit value unaffected.
Bits
Name
Type
Name and Description
Default
7
POL_CLREV1
R/W
Clear Sticky Latch.
This bit enables the EVENT_1 pin
to drive out and clear a sticky latch. This bit is enabled
when set to 1b.
EE(0)
6
POL_LNKEV4
R/W
Link Status.
This bit enables the EVENT_4 pin to act
as link status input. When it is enabled, the EVENT_4
status is only latched if the event is active for five to ten
seconds, and packet transmission is valid only when
link is good.
EE(0)
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