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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 23/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
19
Networking Silicon — Alert on LAN* ASIC
4.5
Register 3h; Event Mask
The Event Mask register is used to mask events from transmitting SOS packets. If the event bit is
set to 1b, the event will cause an SOS packet. If it is 0b, it will not. This mask also prevents the
event from showing up in the status byte in the packet when the bit is 0b.
Note:
The Watchdog event is masked by hardware when the PWR_GOOD signal is low.
4.6
Register 4h; SMI Mask
The SMI Mask register is used to mask events from causing an System Management Interrupt
(SMI). If the event bit is set to 1b, the event will cause an SMI. If it is set to 0b, it will not.
5
Reserved
RO
This bit is reserved and should be set to 0b.
0b
4
POL_EV5
R/W
Event_5 Polarity.
1 = Active High 0 = Active Low
EE(0)
3
POL_EV4
R/W
Event_4 Polarity.
1 = Active High 0 = Active Low
EE(0)
2
POL_EV3
R/W
Event_3 Polarity.
1 = Active High 0 = Active Low
EE(0)
1
POL_EV2
R/W
Event_2 Polarity.
1 = Active High 0 = Active Low
EE(0)
0
POL_EV1
R/W
Event_1 Polarity.
1 = Active High 0 = Active Low
EE(0)
Bits
Name
Type
Name and Description
Default
Bits
Name
Type
Name and Description
Default
7
Reserved
RO
This bit is reserved and should be set to 0b.
0b
6
MSK_WDG
R/W
Watchdog Event Mask.
1 = Watchdog Timer packet
enabled
EE(0)
5
Reserved
R/W
This bit is reserved and should be set to 0b.
EE(0)
4
MSK_EV5
R/W
Event_5 Mask.
1 = Event_5 transmit packet enabled
EE(0)
3
MSK_EV4
R/W
Event_4 Mask.
1 = Event_4 transmit packet enabled
EE(0)
2
MSK_EV3
R/W
Event_3 Mask.
1 = Event_3 transmit packet enabled
EE(0)
1
MSK_EV2
R/W
Event_2 Mask.
1 = Event_2 transmit packet enabled
EE(0)
0
MSK_EV1
R/W
Event_1 Mask.
1 = Event_1 transmit packet enabled
EE(0)
Bits
Name
Type
Name and Description
Default
7
Reserved
RO
This bit is reserved and should be set to 0b.
0b
6
SMI_WDG
R/W
Watchdog Event SMI Mask.
1 = Watchdog Timer SMI
enabled
EE(0)
5
Reserved
R/W
This bit is reserved and should be set to 0b.
0b
4
SMI_EV5
R/W
Event_5 SMI Mask.
1 = Event_5 SMI enabled
EE(0)
3
SMI_EV4
R/W
Event_4 SMI Mask.
1 = Event_4 SMI enabled
EE(0)
2
SMI_EV3
R/W
Event_3 SMI Mask.
1 = Event_3 SMI enabled
EE(0)
1
SMI_EV2
R/W
Event_2 SMI Mask.
1 = Event_2 SMI enabled
EE(0)
0
SMI_EV1
R/W
Event_1 SMI Mask.
1 = Event_1 SMI enabled
EE(0)
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