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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 27/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
23
Networking Silicon — Alert on LAN* ASIC
4.13
Register Bh; Software Status Byte 2
The Software Byte 2 register is used to provide detailed software information to the packet
recipient. This byte provides a method of sending specific information from the software and is
transmitted with each packet. It is intended to be valid when the Software Event bit is set in the
Event Status register.
4.14
Register Ch; EEPROM Access
The EEPROM register is used to give EEPROM status and allow access to the individual EEPROM
pins. EEPROM read complete status and invalid checksum status are indicated in this register. A
GPIO bit interface is provided to allow software to access and write directly to the EEPROM.
4.15
Register Dh; Test Mode
The Test Mode register is used to access internal test modes of the Alert on LAN ASIC and to force
a software reset of the ASIC.
Bits
Name
Type
Name and Description
Default
7:0
SWS2_DAT
R/W
These bits indicate the status of transmitted SOS
packets from a Software Event.
00h
Bits
Name
Type
Name and Description
Default
7
EE_COMP
RO
EEPROM Read Complete Indication.
This bit is set to
1b after the configuration EEPROM read is complete.
0b
6
EE_ICKSM
RO
EEPROM Invalid Checksum Indication.
This bit
should only be read after the EEPROM read has been
completed.
1 = Invalid checksum detected
1b
a
5:4
Reserved
RO
These bits are reserved and should be set to 00b.
00b
3
EE_DO
RO
EEDO Input State.
This bit indicates EE_DO status.
Xb
2
EE_DI
R/W
EEDI Output State.
This bit sets EE_DI status.
0b
1
EE_CS
R/W
EECS Output State.
This bit sets EE_CS status.
0b
0
EE_SK
R/W
EESK Output State.
This bit sets EE_SK status.
0b
a. The default value of EE_ICKSM is 1b after reset. After valid data has been detected, EE_ICKSM is set to 0b, valid checksum
detected.
Bits
Name
Type
Name and Description
Default
7
TST_RST
R/W
SC
Alert on LAN Software Reset.
This bit is used to reset
the Alert on LAN. It performs the equivalent of a
hardware reset and re-reads the EEPROM. This bit
self-clears and the reset completes after four clock
cycles.
0b
6
TST_MODE
R/W
Test Mode.
The Test Mode enable bit provides access
into the Alert on LAN ASIC’s Vector Test Mode
coverage.
0b
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