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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 21/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
17
Networking Silicon — Alert on LAN* ASIC
4.0
Configuration and Status Registers
The Alert on LAN ASIC configuration and status registers are accessible through the SMB. The
SMB cycles for register reads and writes are shown below.
4.1
Register Bit Types
4.2
Register 0h; Revision ID
The Revision ID register identifies the Alert on LAN ASIC and its silicon revision. It is intended to
provide software a method of accessing this information.
4.3
Register 1h; Event Status
The Event Status register holds the status of all events. The watchdog event and events one through
five are set when the event occurs and remain set until software clears them by writing a 1b to the
event status bit. The Software Event, bit 7, is set via software causing an event and self-clears after
three packet transmissions. However, writing a 1b to the Software Event bit always causes a new
packet to be started, regardless of how many packets have been transmitted. If software wants to
send only one packet before it causes a new Software Event, it may monitor the packet retry
counter in the Retransmission Count field (CTL_RTCNT) in the Control register. When STA_EV1
Figure 2. SMB Register Read and Write Cycle
S
AP Address
XXXXRR
A
AP Address
A
RXByte
/A
P
0
S
AP Address
XXXXRRRR
A
TX Byte
P
0
A
S
1
Read Byte:
Write Byte:
A
A
Symbol
Description
R/W
Read/Write
RO
Read Only
SC
Self Clearing
R/W1
Read/Write 1b to clear
EE(x)
Default value from EEPROM with a value of ‘x if the EEPROM is invalid
HWRST
Hardware Reset only (software reset has no effect)
Bits
Name
Type
Name and Description
Default
7:3
AP_ID
RO
Alert on LAN ID.
This register contains the 11010b
binary code identifying the Alert on LAN ASIC.
11010b
2:0
AP_REV
RO
Alert on LAN Silicon Revision.
This register contains
the three bit coded silicon revision.
XXXb
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