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| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 8/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Alert on LAN* ASIC — Networking Silicon
4
Datasheet
The Alert on LAN Software Reset (TST_RST) bit in the Test Mode register is set (
Section
4.15, “Register Dh; Test Mode” on page 23
).
If a TCO transaction is aborted by any of the above mechanisms, except the TST_RST bit, the
Alert on LAN ASIC will retry the transaction or start a new transaction with the prior status
information when the condition that caused the abort no longer exists.
The TCO Status (TSTATUS#) signal is a pulse that indicates that the 82558B has completely
processed the command. In the case of a Transmit command, this signal indicates that the packet
has been sent on the wire or has been aborted due to transmission errors. This signal indicates to the
Alert on LAN ASIC that the TFORCE signal should be de-asserted until the end of the TCO cycle.
The basic flow for a TCO cycle is:
1. The Alert on LAN ASIC samples the TACTIVE pin, which should be low prior to any TCO
cycle. If it is sampled low, the ASIC asserts TFORCE to the 82558B.
2. The Alert on LAN ASIC asserts TRDREQ and transfers one byte (a command byte) and
TMARKER to the 82558B at least two clock cycles after TFORCE was asserted.
3. The 82558B asserts TACTIVE upon completion of sampling the data.
4. The Alert on LAN ASIC samples TACTIVE high and de-asserts TRDREQ.
5. After the data is read by the 82558B and TRDREQ is de-asserted, the 82558B de-asserts
TACTIVE.
6. The Alert on LAN ASIC repeats steps two through five for all bytes in a frame with
TMARKER inactive for data bytes.
7. After the Alert on LAN ASIC has completed transferring a whole frame, it de-asserts the
TFORCE pin.
The following diagram illustrates TCO timing for the Alert on LAN ASIC.
Figure 1. TCO Timing Diagram
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