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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 35/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
31
Networking Silicon — Alert on LAN* ASIC
8.0
Appendix A: Alert on LAN Supporting Hardware
The Alert on LAN ASIC is not a stand alone device. It requires additional components to create a
functional management solution. One
possible
set of supporting hardware is identified in this
appendix.
Note:
Supporting hardware sets will differ from implementation to implementation.
82558 B-step device
The 82558 Ethernet LAN Controller is required for a complete solution. The Alert on
LAN ASIC is designed to communicate with the proprietary TCO interface of the
82558B. The 82558B provides the functionality to transmit data on the network and
calculates and adds a 32-bit CRC to the data packet from the Alert on LAN ASIC.
64x16 1 MHz EEPROM
The Alert on LAN ASIC is designed to use a 64x16 1 MHz EEPROM to configure the
default settings upon reset and hard G2 transitions. If an EEPROM is not present or
contains an invalid checksum, the Alert on LAN ASIC defaults to its component default
settings as defined in section
Section 4.0, “Configuration and Status Registers” on
page 17
.
Note
: The Alert on LAN ASIC requires the use of an EEPROM for its configuration
settings; this is a separate EEPROM from the 82558B’s EEPROM.
Environmental integrated circuit
An environmental IC that is capable of monitoring voltage, temperature, and cover tamper
can be used as part of the system management solution. However, only one input signal on
the Alert on LAN ASIC exists (EVENT_2). If voltage is out of specification, the Alert on
LAN ASIC expects to receive an event on the EVENT_2 signal. The Alert on LAN uses
two other inputs, EVENT_3 (BTI Temperature) and EVENT_1 (Cover Tamper), to
monitor these other events. This is required since the Alert on LAN ASIC does not have
the ability to distinguish the difference between temperature and voltage events over one
input signal.
PIIX4 or equivalent
The PCI-to-ISA/IDE Xcelerator (PIIX4) provides the SMB master interface that enables
the system BIOS and OS to communicate with the Alert on LAN ASIC. PIIX4 also
provides the PWR_GOOD and PCI_RST# signals that propagate to the Alert on LAN
ASIC.
Note
: The PIIX4 has the ability to force the system into a low power state without prior
indication to software. This is the reason the Alert on LAN ASIC monitors PWR_GOOD
for a hard G2 transition.
Sticky latch (optional)
Sticky latches can are useful for detecting events that occur when the system is in a G3 state
(completely off), such as Cover Tamper input. The latch can be battery-backed so that the
Alert on LAN ASIC will become aware that an event occurred when it is powered-up. A sticky
latch also provides the ability to be reset by driving the opposite polarity to the latch on the
bidirectional pin, EVENT_1, of the Alert on LAN ASIC. The EVENT_1 pin of the Alert on
LAN ASIC has the ability to clear a sticky latch. If this feature is enabled, it is executed by
clearing the STA_EV1 bit in the Event Status register. The result is at least a 20 ms output
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