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参数资料
| 型号： | Alert on LAN ASIC |
| 厂商： | Intel Corp. |
| 英文描述： | System Monitoring Instrumentation Device(系统监控指示设备) |
| 中文描述： | 系统监测仪器设备（系统监控指示设备） |
| 文件页数： | 29/36页 |
| 文件大小： | 231K |
| 代理商： | ALERT ON LAN ASIC |
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Datasheet
25
Networking Silicon — Alert on LAN* ASIC
5.0
Reset and Test Modes
5.1
Reset Mode
When the Alert on LAN ASIC’s AUX_GOOD signal is asserted (active low), all internal circuits
are reset, except for the test mode circuitry. The AUX_GOOD signal is expected to remain low for
at least 10 B25_CLK cycles before it is completely reset and stable.
The PCI Reset signal (PCI_RST#) does not reset the Alert on LAN ASIC. However, it is passed
through to the 82558 Reset signal (82558_RST#) when PWR_GOOD is active. When
PWR_GOOD is de-asserted, the 82558_RST# is driven high (inactive).
5.2
Manufacturing Test Mode
The Alert on LAN ASIC is put into Test Mode when the TDATA7 (TEST_EN) signal, pin 13, is
sampled high on the rising edge of reset (AUX_GOOD = 0b). Also, the value of TDATA6
(TEST_MODE) is latched internal to Alert on LAN ASIC. The value of this latched signal
determines the test mode that is activated (while TEST_EN is asserted). The two test modes
supported are:
NANDTREE
TDATA6 latched value = 0b
TRI-STATE
TDATA6 latched value = 1b
The test mode remains enabled until another reset occurs where TDATA7 is sampled low on the
rising edge of reset.
5.2.1
NAND Tree
This test mode provides a NAND tree path around the periphery of Alert on LAN ASIC consisting
of all of the Alert on LAN ASIC pin inputs as stimuli.
The first input on the NAND tree is PCI_RST#, pin 32, and the output of the NAND tree is
ISOLATE#, pin 33.
The NAND tree travels clockwise around the chip (decreasing pin order), including every input
buffer, with the exception of the AUX_GOOD, B25_CLK, and TDATA6 pins.
AUX_GOOD cannot be used as part of the NAND tree because it is used as reset, and B25_CLK
has a special input buffer that cannot use the NAND tree. During the test mode, TDATA6 is used as
a required dedicated input to the process monitor.
All input buffers are true buffers except for PCI_CLK, which is in inverting input buffer. This
should be taken into consideration when implementing the test vectors.
5.2.2
Tri-State
This test mode tri-states all outputs on the Alert on LAN ASIC as well as disables all internal pull-
up and pull-down resistors.
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