参数资料
型号: BR25S128GUZ-WE2
厂商: Rohm Semiconductor
文件页数: 14/26页
文件大小: 0K
描述: IC EEPROM SPI 128KB 12-WLCSP
标准包装: 1
格式 - 存储器: EEPROMs - 串行
存储器类型: EEPROM
存储容量: 128K (16K x 8)
速度: 10MHz
接口: SPI 3 线串行
电源电压: 1.7 V ~ 5.5 V
工作温度: -40°C ~ 85°C
封装/外壳: 12-XFBGA,CSPBGA
供应商设备封装: VCSP35L2
包装: 标准包装
其它名称: BR25S128GUZ-WE2DKR
BR25S128GUZ-W
(128K)
Datasheet
3. Write command (WRITE)
CSB
~~
~~
~~
SCK
0
1
2
3
4
5
6
7
8
9
10
11 ~ ~
23
24
30
31
~~
~~
SI
0
0
0
0
0
0
1
0
*
*
A13
A12 ~ ~
A1
A0
D7
D6
~~
D2
D1
D0
SO
High-Z
~~
* =Don't Care
Figure 33. Write command
By write command, data of EEPROM can be written. As for this command, set CSB LOW, then input address and data
after write ope code. Then, by making CSB HIGH, the EEPROM starts writing. The write time of EEPROM requires time of
tE/W (Max 5ms). During tE/W, other than read status register command is not accepted. Set CSB HIGH between taking
the last data (D0) and rising the next SCK clock. At the other timing, write command is not executed, and this write
command is cancelled. This IC has page write function, and after input of data for 1 byte (8 bits), by continuing data input
without setting CSB HIGH, 2byte or more data can be written for one tE/W. Up to 64 arbitrary bytes can be written. In page
write, the insignificant 6 bit of the designated address is incremented internally at every time when data of 1 byte is input
and data is written to respective addresses. When data of the maximum bytes or higher is input, address rolls over, and
previously input data is overwritten.
4. Read status register command (RDSR)
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
bit7
bit6
bit5
bit4
bit3
bit2
bit1
bit0
SI
0
0
0
0
0
0
0
1
WPEN
*
*
*
BP1 BP0
*
*
SO
High-Z
*=Don't care
Figure 34. Write status register
Write status register command can write data of status register. The data can be written by this command are 3 bits, that is,
WPEN (bit7), BP1 (bit3) and BP0 (bit2) among 8 bits of status register. By BP1 and BP0, write disable block of EEPROM
can be set. As for this command, set CSB LOW, and input ope code of write status register, and input data. Then, by
making CSB HIGH, EEPROM starts writing. Write time requires time of tE/W as same as write. As for CSB rise, set CSB
HIGH between taking the last data bit (bit0) and the next SCK clock rising. At the other timing, command is cancelled.
Write disable block is determined by BP1 BP0, and the block can be selected from 1/4 , 1/2, and entire of memory array
(Refer to the write disable block setting table.). To the write disabled block, write cannot be made, and only read can be
made.
CSB
SCK
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
SI
SO
0
High-Z
0
0
0
0
1
0
1
bit7
WPEN
bit6
0
bit5
0
bit4
0
bit3
bit2
bit1
bit0
BP1 BP0 WEN R/B
Figure 35. Read status register command
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?2012 ROHM Co., Ltd. All rights reserved.
TSZ22111 ? 15 ? 001
14/23
TSZ02201-0R2R0G100310-1-2
19.Jul.2012 Rev.001
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