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| 型号： | BX805555030P |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封装： | LGA-771 |
| 文件页数： | 21/104页 |
| 文件大小： | 3690K |
| 代理商： | BX805555030P |
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Dual-Core Intel Xeon Processor 5000 Series Datasheet
23
Electrical Specifications
signals are also included. Table 2-8 provides signal reference voltages.
Notes:
1.
Signals that do not have RTT, nor are actively driven to their high voltage level.
2.
The on-die termination for these signals is not RTT. TCK, TDI, and TMS have an approximately 150 KΩ
pullup to VTT.
Notes:
1.
These signals also have hysteresis added to the reference voltage. See Table 2-14 for more information.
2.
Use Table 2-15 for signal FORCEPR# specifications.
2.8
GTL+ Asynchronous and AGTL+ Asynchronous
Signals
Input signals such as A20M#, FORCEPR#, IGNNE#, INIT#, LINT0/INTR, LINT1/NMI,
SMI# and STPCLK# utilize GTL+ input buffers. Legacy output FERR#/PBE# and other
non-AGTL+ signals IERR#, THERMTRIP# and PROCHOT# utilize GTL+ output buffers.
All of these asynchronous GTL+ signals follow the same DC requirements as AGTL+
signals; however, the outputs are not driven high (during the electrical 0-to-1
transition) by the processor. FERR#/PBE#, IERR#, and IGNNE# have now been defined
as AGTL+ asynchronous signals as they include an active p-MOS device. Asynchronous
GTL+ and asynchronous AGTL+ signals do not have setup or hold time specifications in
relation to BCLK[1:0]; however, all of the asynchronous GTL+ and asynchronous
AGTL+ signals are required to be asserted/deasserted for at least six BCLKs in order for
the processor to recognize them. See Table 2-15 for the DC specifications for the
asynchronous GTL+ signal groups.
2.9
Test Access Port (TAP) Connection
Due to the voltage levels supported by other components in the Test Access Port (TAP)
logic, it is recommended that the processor(s) be first in the TAP chain and followed by
any other components within the system. A translation buffer should be used to
Table 2-7.
Signal Description Table
Signals with RTT
Signals with no RTT
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPRI#, COMP[7:4], D[63:0]#, DBI[3:0]#,
DBSY#, DEFER#, DP[3:0]#, DRDY#, DSTBN[3:0]#,
DSTBP[3:0]#, FORCEPR#, HIT#, HITM#, LOCK#,
MCERR#, PROCHOT#, REQ[4:0]#, RS[2:0]#,
RSP#, TCK2, TDI2, TEST_BUS, TMS2, TRDY#,
TRST#2
A20M#, BCLK[1:0], BPM[5:0]#, BR[1:0]#, BSEL[2:0],
COMP[3:0], FERR#/PBE#, GTLREF_ADD_C[1:0],
GTLREF_DATA_C[1:0], IERR#, IGNNE#, INIT#, LINT0/
INTR, LINT1/NMI, LL_ID[1:0], MS_ID[1:0], PWRGOOD,
RESET#, SKTOCC#, SMI#, STPCLK#, TDO,
TESTHI[11:0], THERMDA, THERMDA2, THERMDC,
THERMDC2, THERMTRIP#, VCC_DIE_SENSE,
VCC_DIE_SENSE2, VID[5:0], VID_SELECT,
VSS_DIE_SENSE, VSS_DIE_SENSE2, VTTPWRGD
Open Drain Signals1
BPM[5:0]#, BR0#, FERR#/PBE#, IERR#, PROCHOT#, TDO, THERMTRIP#
Table 2-8.
Signal Reference Voltages
GTLREF
VTT / 2
A[35:3]#, ADS#, ADSTB[1:0]#, AP[1:0]#, BINIT#,
BNR#, BPM[5:0]#, BPRI#, BR[1:0]#, D[63:0]#,
DBI[3:0]#, DBSY#, DEFER#, DP[3:0]#, DRDY#,
DSTBN[3:0]#, DSTBP[3:0]#, FORCEPR#2, HIT#,
HITM#, IERR#, LINT0/INTR, LINT1/NMI, LOCK#,
MCERR#, RESET#, REQ[4:0]#, RS[2:0]#, RSP#,
TRDY#
A20M#, IGNNE#, INIT#, PWRGOOD1, SMI#, STPCLK#,
TCK1, TDI1, TMS1, TRST#1, VTTPWRGD
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相关代理商/技术参数 |
参数描述 |
|---|---|
| BX805555050A S L96C | 制造商:Intel 功能描述:XEON PROCESSOR 5050 |
| BX805555060A S L96A | 制造商:Intel 功能描述:MPU Xeon 65nm 3.2GHz 771-Pin FCLGA6 |
| BX805555060P S L96A | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5060 65nm 3.2GHz 771-Pin FCLGA6 |
| BX805565120P S L9RY | 制造商:Intel 功能描述:MPU Xeon 制造商:Intel 功能描述:MPU Xeon? Processor 5120 RISC 64-Bit 65nm 1.86GHz 771-Pin LGA Box |
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