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| 型号： | BX805555030P |
| 厂商： | INTEL CORP |
| 元件分类： | 微控制器/微处理器 |
| 英文描述： | 64-BIT, MICROPROCESSOR, BGA771 |
| 封装： | LGA-771 |
| 文件页数： | 30/104页 |
| 文件大小： | 3690K |
| 代理商： | BX805555030P |
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Dual-Core Intel Xeon Processor 5000 Series Datasheet
31
Electrical Specifications
Notes:
1.
Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.
All outputs are open drain.
3.
VHYS represents the amount of hysteresis, nominally centered about 0.5 * VTT for all PWRGOOD and TAP
inputs.
4.
PWRGOOD input and the TAP signal group must meet system signal quality specification in Section 3.
5.
The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
Notes:
1.Unless otherwise noted, all specifications in this table apply to all processor frequencies.
2.All outputs are open drain.
3.VIL is defined as the voltage range at a receiving agent that will be interpreted as a logical low value.
4.VIH is defined as the voltage range at a receiving agent that will be interpreted as a logical high value.
5.VIH and VOH may experience excursions above VTT. However, input signal drivers must comply with the signal
quality specifications in Section 3.
6.Refer to the processor HSPICE* I/O Buffer Models for I/V characteristics.
7.The VTT referred to in these specifications refers to instantaneous VTT.
8.The maximum output current is based on maximum current handling capability of the buffer and is not
specified into the test load.
9.Leakage to VSS with land held at VTT.
10.Leakage to VTT with land held at 300 mV.
11.LINT0/INTR and LINT1/NMI use GTLREF_ADD as a reference voltage. For these two signals VIH =
GTLREF_ADD + (0.10 * VTT) and VIL= GTLREF_ADD - (0.10 * VTT).
2.12.1
VCC Overshoot Specification
The Dual-Core Intel Xeon Processor 5000 series can tolerate short transient overshoot
events where VCC exceeds the VID voltage when transitioning from a high-to-low
current load condition. This overshoot cannot exceed VID + VOS_MAX (VOS_MAX is the
ILI
Input Leakage Current
N/A
± 200
A
ILO
Output Leakage Current
N/A
± 200
A
RON
Buffer On Resistance
7
11
Ω
5
Table 2-14. PWRGOOD Input and TAP Signal Group DC Specifications (Sheet 2 of 2)
Symbol
Parameter
Min
Max
Unit
Notes 1,
2
Table 2-15. GTL+ Asynchronous and AGTL+ Asynchronous Signal Group
DC Specifications
Symbol
Parameter
Min
Max
Unit
Notes1
VIL
Input Low Voltage
0.0
(0.5 * VTT) - (0.10 * VTT)
V
3, 11
VIH
Input High Voltage
(0.5 * VTT) + (0.10 * VTT)VTT
V
4, 5, 7,
11
VOH
Output High Voltage
0.90*VTT
VTT
V2, 5, 7
IOL
Output Low Current
-
VTT/
[(0.50*RTT_MIN)+(RON_MIN)]
A8
ILI
Input Leakage Current
N/A
± 200
A
9
ILO
Output Leakage
Current
N/A
± 200
A
10
RON
Buffer On Resistance
7
11
Ω
6
Table 2-16. VTTPWRGD DC Specifications
Symbol
Parameter
Min
Max
Unit
VIL
Input Low Voltage
0.0
0.30
V
VIH
Input High Voltage
0.90
VTT
V
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相关代理商/技术参数 |
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|---|---|
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