参数资料
型号: CDB4245
厂商: Cirrus Logic Inc
文件页数: 34/59页
文件大小: 0K
描述: BOARD EVAL FOR CS4245 CODEC
标准包装: 1
主要目的: 音频编解码器
嵌入式: 是,FPGA / CPLD
已用 IC / 零件: CS4245
主要属性: 4 个单端模拟和 1 个麦克风输入和 8 个输出,S/PDIF 发射器和接收器
次要属性: 图形用户界面
已供物品:
产品目录页面: 754 (CN2011-ZH PDF)
相关产品: CS4245-DQZR-ND - IC CODEC AUD STER 104DB 48-LQFP
598-1616-ND - IC CODEC AUD STER 104DB 48LQFP
598-1034-ND - IC CODEC AUD STER 104DB 48LQFP
其它名称: 598-1501
CS4245
4.4
Analog Input Multiplexer, PGA, and Mic Gain
The CS4245 contains a stereo 6-to-1 analog input multiplexer followed by a programmable gain amplifier
(PGA). The input multiplexer can select one of six possible stereo analog input sources and route it to the
PGA. Analog inputs 4A and 4B are able to insert a +32 dB gain stage before the input multiplexer, allowing
them to be used for microphone-level signals without the need for any external gain. The PGA stage pro-
vides ? 12 dB of gain or attenuation in 0.5 dB steps. Figure 14 shows the architecture of the input multiplex-
er, PGA, and microphone gain stages. .
AIN1A
AIN2A
AIN3A
AIN4A/MICIN1
+32 dB
MUX
PGA
Out to ADC
Channel A
AIN5A
AIN6A
AIN1B
AIN2B
AIN3B
Analog Input
Selection Bits
Channel A
PGA Gain Bits
Channel B
PGA Gain Bits
AIN4B/MICIN2
+32 dB
MUX
PGA
Out to ADC
Channel B
AIN5B
AIN6B
Figure 14. Analog Input Architecture
The “Analog Input Selection (Bits 2:0)” on page 48 outlines the bit settings n ecessary to control the input
multiplexer and mic gain. “Channel B PGA Control - Address 07h” on page 47 and “Channel A PGA Control
- Address 08h” on pa ge 47 outline the register settings necessary to control the PGA. By de fault, line-
level input 1 is selected, and the PGA is set to 0 dB.
4.5
4.6
34
Input Connections
The analog modulator samples the input at 6.144 MHz (MCLK=12.288 MHz). The digital filter will reject sig-
nals within the stopb and of the f ilter. However, there is no rejection for input signals which a re
(n ? 6.144 MHz) the digital passband frequency, where n=0,1,2,... Refer to the Typical Connection Diagram
for the recommended analog input circuit that will attenuate noise energy at 6.144 MHz. The use of capac-
itors which ha ve a larg e voltage coefficient (such as general-purpose ceramics) must be avoid ed since
these can degrade signal linearity. Any unused analog input pairs should be left unconnected.
Output Connections
The CS4245 DACs implement a switched-capacitor filter, followed by a continuous time low-pass filter. Its
response, combined with tha t of the digital interpolator, is sh own in Section 8. “DAC Filter Plots” on
page53 ”.TherecommendedexternalanalogcircuitryisshownintheTypicalConnectionDiagram.
The CS4245 DAC does not include phase or amplitude compensation for an external filter. Therefore, the
DAC system phase and amplitude response is dependent on the external analog circuitry.
DS656F3
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