参数资料
| 型号： | CS61584A-IQ3Z |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 18/47页 |
| 文件大小： | 0K |
| 描述： | IC LINE INTERFACE T1/E1 64LQFP |
| 标准包装： | 160 |
| 接口： | 并行/串行 |
| 电源电压： | 3.3V，5V |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1713 |
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CS61584A
DS261PP5
25
DS261PP5
Latched-AIS: Set high on the rising edge of the
alarm indication signal condition. Reading the Sta-
tus register clears the Latched-AIS bit and deacti-
vates the INT pin. Refer to the timing diagram in
Figure 18.
Latched-BPV: Indicates a bipolar violation has
been received since the last read of the Status reg-
ister. Reading the Status register clears the
Latched-BPV bit and deactivates the INT pin. This
bit is set only when the line code decoder is enabled
in the Control A register.
Latched-Overflow: Indicates a waveform generat-
ed using the Arbitrary Waveform register has ex-
ceeded full scale since the last read of the Status
register. Reading the Status register clears the
Latched-Overflow bit and deactivates the INT pin.
Latched-Reset: Indicates a reset event (power-up or
RESET pin) has occurred since the last read of the
Status register. Reading the Status register clears
the Latched-Reset bit and deactivates the INT pin.
This bit is not maskable.
Latched-CLKLOST: Set high when TCLK or REF-
CLK are absent. Reading the Status register clears
the Latched-CLKLOST bit and deactivates the INT
pin.
Interrupt: Indicates a change in the Status register
since the last read. Reading the Status register
clears the Interrupt bit and deactivates the INT pin.
9.1.2
Mask Registers
The Mask registers are read-write registers and are
shown in Table 6. The Mask registers disables the
interrupts in the corresponding Status register on a
per-bit basis. Masking a Status register bit forces it
to remain at zero and prevents the INT pin from ac-
tivating on the condition.
Mask Register (Channel 1)
Serial Port Address: 0x12; Parallel Port Address: 0xY2
Bit
Description
Definition
Reset
Value
10
7
Mask LOS1
Mask Interrupt
Enable Interrupt
0
6
Mask Latched-LOS1
Mask Interrupt
Enable Interrupt
0
5
Mask AIS1
Mask Interrupt
Enable Interrupt
0
4
Mask Latched-AIS1
Mask Interrupt
Enable Interrupt
0
3
Mask Latched-BPV1
Mask Interrupt
Enable Interrupt
0
2
Mask Latched-Overflow1
Mask Interrupt
Enable Interrupt
0
1
Automatic All Ones, AAO
Ones at RPOS/NEG on LOS
Zeros at RPOS/NEG on LOS
0
Mask Interrupt1
Mask Interrupt
Enable Interrupt
0
Mask Register (Channel 2)
Serial Port Address: 0x13; Parallel Port Address: 0xY3
Bit
Description
Definition
Reset
Value
10
7
Mask LOS2
Mask Interrupt
Enable Interrupt
0
6
Mask Latched-LOS2
Mask Interrupt
Enable Interrupt
0
5
Mask AIS2
Mask Interrupt
Enable Interrupt
0
4
Mask Latched-AIS2
Mask Interrupt
Enable Interrupt
0
3
Mask Latched-BPV2
Mask Interrupt
Enable Interrupt
0
2
Mask Latched-Overflow2
Mask Interrupt
Enable Interrupt
0
1
Mask Latched-CLKLOST
Mask Interrupt
Enable Interrupt
0
Mask Interrupt2
Mask Interrupt
Enable Interrupt
0
Table 6. Mask Registers
CS61584A
DS261F1
25
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS61584A-IQ3ZR | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5 | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5Z | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5ZR | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584-IL3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Line Interface |
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