参数资料
| 型号： | CS61584A-IQ3Z |
| 厂商： | Cirrus Logic Inc |
| 文件页数： | 36/47页 |
| 文件大小： | 0K |
| 描述： | IC LINE INTERFACE T1/E1 64LQFP |
| 标准包装： | 160 |
| 接口： | 并行/串行 |
| 电源电压： | 3.3V，5V |
| 封装/外壳： | 64-LQFP |
| 供应商设备封装： | 64-LQFP（10x10） |
| 包装： | 托盘 |
| 安装类型： | 表面贴装 |
| 产品目录页面： | 759 (CN2011-ZH PDF) |
| 其它名称： | 598-1713 |
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CS61584A
DS261PP5
41
DS261PP5
T1/E1 Data Inputs and Outputs
RCLK1, RCLK2 - Receive Clock (PLCC pins 10, 59; TQFP pins 1, 48)
RPOS1, RPOS2 - Receive Positive Data (PLCC pins 11, 58; TQFP pins 2, 47)
RNEG1, RNEG2 - Receive Negative Data (PLCC pins 12, 57; TQFP pins 3, 46)
The receiver recovered clock and NRZ digital data from RTIP and RRING is output on these pins.
During Hardware mode operation, the CLKE pin determines the clock edge on which RPOS and RNEG
are stable and valid. During Host mode operation, the CLKE bit in the Control A register determines the
clock edge on which RPOS and RNEG are stable and valid. A positive pulse (with respect to ground)
received on RTIP generates a logic 1 on RPOS, and a positive pulse received on RRING generates a
logic 1 on RNEG.
RDATA1, RDATA2 - Receive Data [Host mode] (PLCC pins 11, 58; TQFP pins 2, 47)
During Host mode operation with the coders enabled, the decoded digital data stream from RTIP and
RRING is output on RDATA in NRZ format. The CLKE bit in the Control A register determines the clock
edge on which RDATA is stable and valid.
RTIP1, RTIP2 - Receive Tip (PLCC pins 27, 42; TQFP pins 17, 32)
RRING1, RRING2 - Receive Ring (PLCC pins 28, 41; TQFP pins 18, 31)
The receive AMI signal from the line interface is input on these pins. The recovered clock and data are
output on RCLK, RPOS, and RNEG (or RDATA).
TCLK1, TCLK2 - Transmit Clock (PLCC pins 13, 56; TQFP pins 4, 45)
TPOS1, TPOS2 - Transmit Positive Data (PLCC pins 14, 55; TQFP pins 5, 44)
TNEG1, TNEG2 - Transmit Negative Data (PLCC pins 15, 54; TQFP pins 6, 43)
The transmit clock and data are input to these pins. The signal is driven to the line interface at TTIP
and TRING. Data on TPOS and TNEG are sampled on the falling edge of TCLK. An input on TPOS
causes a positive pulse to be transmitted at TTIP and TRING, while an input on TNEG causes a
negative pulse to be transmitted at TTIP and TRING.
TDATA1, TDATA2 - Transmit Data [Host mode] (PLCC pins 14, 55; TQFP pins 5, 44)
During Host mode operation with the coders enabled, the un-encoded digital data stream is input on
TDATA in NRZ format. Data at TDATA is sampled on the falling edge of TCLK.
TTIP1, TTIP2 - Transmit Tip (PLCC pins 20,49; TQFP pins 11, 38)
TRING1, TRING2 - Transmit Ring (PLCC pins 23, 46; TQFP pins 14, 35)
The transmit AMI signal to the line interface is output on these pins. The transmit clock and data are
input on TCLK, TPOS, and TNEG (or TDATA).
Oscillator
1XCLK - One-times Clock Frequency Select (PLCC pin 38; TQFP pin 28)
When 1XCLK is high, REFCLK must be a 1X clock (i.e., 1.544 MHz for T1 applications or 2.048 MHz
for E1 applications). When 1XCLK is low, REFCLK must be an 8X clock (i.e., 12.352 MHz for T1
applications or 16.384 MHz for E1 applications).
CS61584A
DS261F1
41
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相关代理商/技术参数 |
参数描述 |
|---|---|
| CS61584A-IQ3ZR | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5 | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5Z | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dual T1/ E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584A-IQ5ZR | 功能描述:网络控制器与处理器 IC IC 3.3V/5V Dul T1/E1 Line Intrfc Unit RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| CS61584-IL3 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:Line Interface |
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