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参数资料
| 型号： | DAC5687IPZPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 36/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZPG4 |
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CLK2
DA[15:0]
DB[15:0]
ts(DATA)
th(DATA)
A0
A1
A2
AN
AN+1
A3
B0
B1
B2
BN
BN+1
B3
PLLLOCK
td(PLLLOCK)
T0040-01
CLK2
DA[15:0]
DB[15:0]
ts(DATA)
th(DATA)
A0
A1
A2
AN
AN+1
A3
B0
B1
B2
BN
BN+1
B3
PLLLOCK
td(PLLLOCK)
T0040-02
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
1. PLLVDD = 0 V and dual_clk = 0: EXTERNAL CLOCK MODE
In EXTERNAL CLOCK MODE, the user provides a clock signal at the DAC output sample rate through
CLK2/CLK2C. CLK1/CLK1C and the internal PLL are not used. The LPF and CLK1/CLK1C pins can be left
unconnected. The input data-rate clock and interpolation rate are selected by the bits interp(1:0) in register
CONFIG0 and is output through the PLLLOCK pin. The PLLLOCK clock can be used to drive the input data
source (such as digital upconverter) that sends the data to the DAC. Note that the PLLLOCK delay relative to the
input CLK2 rising edge (td(PLLLOCK) in Figure 43 and Figure 44) increases with increasing loads. The PLLLOCK
output driver is not capable of reaching full speed at lower IOVDD voltages. For example, at IOVDD = 1.8 V,
PLLLOCK output frequencies > 100 MHz are not recommended. The input data is latched on either the rising
(inv_plllock = 0) or falling edge (inv_plllock = 1) of PLLLOCK, which is sensed internally at the output pin.
Figure 43. Dual-Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Rising Edge)
Figure 44. Dual-Bus Mode Timing Diagram for External Clock Mode (PLLLOCK Falling Edge)
2. PLLVDD = 3.3 V (dual_clk can be 0 or 1 and is ignored): PLL CLOCK MODE
In PLL CLOCK MODE, drive the DAC at the input sample rate (unless the data is multiplexed) through
CLK1/CLK1C. CLK2/CLK2C is not used. In this case, there is no phase ambiguity on the clock. The DAC
generates the higher-speed DAC sample-rate clock using an internal PLL/VCO. In PLL clock mode, the user
provides a differential external reference clock on CLK1/CLK1C.
Copyright 2005–2006, Texas Instruments Incorporated
41
Product Folder Link(s): DAC5687
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| DAC5687IPZPR | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687IPZPRG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687MPZPEP | 功能描述:数模转换器- DAC 16B 500Msps 2X-8X Interp 2-Channel DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5688 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
| DAC5688_10 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
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