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参数资料
| 型号： | DAC5687IPZPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 40/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZPG4 |
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Input FIFO
B0166-01
0
1
S
0
1
D Q
Input
Pointer
Generation
PLLLOCK
MUX
CLK1
CLK1C
{PLLVDD,inv_plllock,dual_clk}
MUX
Clock
Generator
Resynchonized
DA[15:0],DB[15:0]
andPHSTR
syncsource
{TXENABLE,PHSTR,QFLAG,DB[15],
DA[15]oneshot,SIFwrite,alwaysoff}
CLK2
CLK2C
PLL VCO
1
fifo_bypass
in_sel_d
in_sel_c
in_sel_b
in_sel_a
q_b
q_c
q_d
q_in
q_out
clk_in
clk_out
sel_q_a
sel_q_d
sel_q_c
sel_q_b
sync
D Q
DA[15:0],
DB[15:0],
PHSTR
0
1
S
D Q
S
0
1
S
D Q
Q
D
0
Q
D
S
q_a
Output
Pointer
Generation
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
When using interleaved input mode with the PLL enabled, input clock CLK1 is at 2
× the frequency of the input to
FIR1. If the dividers for multiple DAC5687s are not synchronized, there can be a one-CLK1-period output time
difference between devices that have synchronized input data. However, the divider that generates the clock for
the FIR1 input is not connected to the DAC5687 synchronization circuitry. In general, dual-clock mode is
recommended in applications where multiple DAC5687s must be synchronized in interleaved input mode. If PLL
mode is required, the following workaround using the asynchronous RESET pin synchronizes the clock dividers.
With the CLK1 input off and the chip powered, set RESET low for >50 ns and then high for all devices,
simultaneously restarting CLK1. Note that the devices must be reprogrammed after the reset sequence. If CLK1
is kept active during the reset sequence, then multiple devices are typically reset to the same clock phase, but
because the RESET pin is asynchronous, the clock divider on two devices can come out of reset at slightly
different times.
In external clock mode, where the DAC5687 is clocked at the DAC update rate, the DAC5687 has an optional
input FIFO that allows latching of DA[15:0], DB[15:0] and PHSTR based on a user-provided CLK1/CLK1C input
or the input data rate clock provided to the PLLLOCK pin. The FIFO can be bypassed by setting register
fifo_bypass in CONFIG0 to 1.
The input interface FIFO incorporates a four-sample register file, an input pointer, and an output pointer.
Initialization of the FIFO pointers can be programmed to one of seven different sources.
Figure 52. DAC5687 Input FIFO Logic
Copyright 2005–2006, Texas Instruments Incorporated
45
Product Folder Link(s): DAC5687
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| DAC5687IPZPR | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687IPZPRG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687MPZPEP | 功能描述:数模转换器- DAC 16B 500Msps 2X-8X Interp 2-Channel DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5688 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
| DAC5688_10 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
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