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参数资料
| 型号： | DAC5687IPZPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 38/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZPG4 |
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t
align +
1
2f
CLK2
* 0.5 ns
th
CLK2
CLK1
DA[15:0]
DB[15:0]
< talign
ts
T000201
th
CLK1
DA[15:0]
DB[15:0]
ts
T015401
Interleave Bus Mode
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
3. PLLVDD = 0 V and dual_clk = 1: DUAL CLOCK MODE
In DUAL CLOCK MODE, the DAC is driven at the DAC sample rate through CLK2/CLK2C and the input data
rate through CLK1/CLK1C. There are two options in dual clock mode: with FIFO (inv_plllock set) and without
FIFO (inv_plllock clear). If the FIFO is not used, the CLK1/CLK1C input is used to set the phase of the internal
clock divider. In this case, the edges of CLK1 and CLK2 must be aligned to within ±talign (Figure 47), defined as
where fCLK2 is the clock frequency at CLK2. For example, talign = 0.5 ns at fCLK2 = 500 MHz and 1.5 ns at fCLK2 =
250 MHz.
If the FIFO is enabled (inv_plllock set) in dual clock mode, then CLK1 is only used as an input latch (Figure 48),
is independent from the internal divided clock generated from CLK2/CLK2C, and there is no alignment
specification. However, the FIFO must be synchronized by one of the methods listed in the SYNC_CNTL
register, and the latency of the DAC can be up to one clock cycle different, depending on the phase relationship
between CLK1 and the internally divided clock.
Figure 47. Dual Clock Mode Without FIFO
Figure 48. Dual Clock Mode With FIFO
The CDC7005 from Texas Instruments is recommended for providing phase-aligned clocks at different
frequencies for this application.
In interleave bus mode, one parallel data stream with interleaved data (I and Q) is input to the DAC5687 on data
bus DA. Interleave bus mode is selected by setting INTERL to 1 in the config_msb register. Figure 49 shows
the DAC5687 data path in interleave bus mode. The interleave bus mode timing diagram is shown in Figure 50.
Copyright 2005–2006, Texas Instruments Incorporated
43
Product Folder Link(s): DAC5687
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| DAC5687IPZPR | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687IPZPRG4 | 功能描述:数模转换器- DAC 16-bit 500 MSPS 2-8x Interpolat’g Dual-Ch RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5687MPZPEP | 功能描述:数模转换器- DAC 16B 500Msps 2X-8X Interp 2-Channel DAC RoHS:否 制造商:Texas Instruments 转换器数量:1 DAC 输出端数量:1 转换速率:2 MSPs 分辨率:16 bit 接口类型:QSPI, SPI, Serial (3-Wire, Microwire) 稳定时间:1 us 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:SOIC-14 封装:Tube |
| DAC5688 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
| DAC5688_10 | 制造商:TI 制造商全称:Texas Instruments 功能描述:DUAL-CHANNEL, 16-BIT, 800 MSPS, 2x-8x INTERPOLATING DIGITAL-TO-ANALOG CONVERTER (DAC) |
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