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参数资料
| 型号： | DAC5687IPZPG4 |
| 厂商： | TEXAS INSTRUMENTS INC |
| 元件分类： | DAC |
| 英文描述： | PARALLEL, WORD INPUT LOADING, 0.0104 us SETTLING TIME, 16-BIT DAC, PQFP100 |
| 封装： | GREEN, PLASTIC, HTQFP-100 |
| 文件页数： | 53/79页 |
| 文件大小： | 2490K |
| 代理商： | DAC5687IPZPG4 |
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Power-Up Sequence
Sleep Mode
APPLICATION INFORMATION
Designing the PLL Loop Filter
SLWS164E – FEBRUARY 2005 – REVISED SEPTEMBER 2006
In all conditions, bring up DVDD first. If PLLVDD is powered (PLL on), CLKVDD should be powered before or
simultaneously with PLLVDD. AVDD, CLKVDD, and IOVDD can be powered simultaneously or in any order.
Within AVDD, the multiple AVDD pins should be powered simultaneously.
There are no specific requirements on the ramp rate for the supplies.
The DAC5687 features a power-down mode that turns off the output current and reduces the supply current to
less than 5 mA over the supply range of 3 V to 3.6 V and temperature range. The power-down mode is activated
by applying a logic level 1 to the SLEEP pin (e.g., by connecting pin SLEEP to AVDD). An internal pulldown
circuit at node SLEEP ensures that the DAC5687 is enabled if the input is left disconnected. Power-up and
power-down activation times depend on the value of external capacitor at node EXTIO. For a nominal capacitor
value of 0.1
F, power down takes less than 5 s and approximately 3 ms to power back up.
Table 15. Optimum DAC5687 PLL Settings
fDAC (MHz)
pll_freq
pll_kv
pll_div(1:0)
fVCO/fDAC
Estimated GVCO (MHz/V)
25 to 28.125
0
11
8
380
28.125 to 46.25
0
1
11
8
250
46.25 to 60
0
11
8
300
60 to 61.875
1
11
8
130
61.875 to 65
1
0
11
8
225
65 to 92.5
0
1
10
4
250
92.5 to 120
0
10
4
300
120 to 123.75
1
10
4
130
123.75 to 130
1
0
10
4
225
130 to 185
0
1
01
2
250
185 to 240
0
01
2
300
240 to 247.5
1
01
2
130
247.5 to 260
1
0
01
2
225
260 to 370
0
1
00
1
250
370 to 480
0
00
1
300
480 to 495
1
00
1
130
495 to 520
1
0
00
1
225
The optimized DAC5687 PLL settings based on the VCO frequency MIN and MAX values (see the digital
specifications) as a function of fDAC are listed in Table 15. To minimize phase noise at a given fDAC, pll_freq,
pll_kv, and pll_div have been chosen so GVCO is minimized and within the MIN and MAX frequency for a given
setting.
For example, if fDAC = 245.76 MHz, pll_freq is set to 1, pll_kv is set to 0 and pll_div(1:0) is set to 01 (divide
by 2) to lock the VCO at 491.52 MHz.
The external loop filter components C1, C2, and R1 are set by the GVCO, N = fVCO/fDATA = fVCO ×
Interpolation/fDAC, the loop phase margin φd and the loop bandwidth ωd. Except for applications where abrupt
clock frequency changes require a fast PLL lock time, it is suggested that
φ
d be set to at least 80 degrees for
stable locking and suppression of the phase-noise side lobes. Phase margins of 60 degrees or less can be
sensitive to board layout and decoupling details.
C1, C2, and R1 are then calculated by the following equations
Copyright 2005–2006, Texas Instruments Incorporated
57
Product Folder Link(s): DAC5687
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