参数资料
型号: DK-DEV-5AGXB3N/ES
厂商: Altera
文件页数: 18/39页
文件大小: 0K
描述: ARRIA V DEVELOPMENT KIT
标准包装: 1
系列: Arria V GX
类型: FPGA
适用于相关产品: Arria? V GX
所含物品: 板,线缆,文档,电源
其它名称: 544-2743
18
Variable-Precision DSP Block
AV-51001
2013.12.26
Table 14: Variable-Precision DSP Block Configurations for Arria V Devices
Usage Example
Low precision fixed point for video
applications
Medium precision fixed point in FIR
filters
FIR filters
Single-precision floating-point
implementations
Very high precision fixed point
Multiplier Size (Bit)
Three 9 x 9
Two 18 x 18
Two 18 x 18 with
accumulate
One 27 x 27
One 36 x 36
DSP Block Resource
1
1
1
1
2
implementations
You can configure each DSP block during compilation as independent three 9 x 9, two 18 x 18, or one 27 x 27
multipliers. Using two DSP block resources, you can also configure a 36 x 36 multiplier for high-precision
applications. With a dedicated 64 bit cascade bus, you can cascade multiple variable-precision DSP blocks
to implement even higher precision DSP functions efficiently.
Table 15: Number of Multipliers in Arria V Devices
The table lists the variable-precision DSP resources by bit precision for each Arria V device.
Variant
Member
Code
Variable-
precision
DSP Block
Independent Input and Output Multiplications
Operator
9x9Multiplier 18 x 18 27 x 27 36 x 36
Multiplier Multiplier Multiplier
18 x 18
Multiplier
Adder
Mode
18 x 18 Multiplier
Adder Summed
with 36 bit Input
A1
A3
A5
240
396
600
720
1,188
1,800
480
792
1,200
240
396
600
240
396
600
240
396
600
Arria V GX
Arria V GT
A7
B1
B3
B5
B7
C3
C7
D3
D7
800
920
1,045
1,092
1,156
396
800
1,045
1,156
2,400
2,760
3,135
3,276
3,468
1,188
2,400
3,135
3,468
1,600
1,840
2,090
2,184
2,312
792
1,600
2,090
2,312
800
920
1,045
1,092
1,156
396
800
1,045
1,156
800
920
1,045
1,092
1,156
396
800
1,045
1,156
800
920
1,045
1,092
1,156
396
800
1,045
1,156
Altera Corporation
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