参数资料
型号: DK-DEV-5AGXB3N/ES
厂商: Altera
文件页数: 27/39页
文件大小: 0K
描述: ARRIA V DEVELOPMENT KIT
标准包装: 1
系列: Arria V GX
类型: FPGA
适用于相关产品: Arria? V GX
所含物品: 板,线缆,文档,电源
其它名称: 544-2743
AV-51001
2013.12.26
PMA Features
27
PMA Features
To prevent core and I/O noise from coupling into the transceivers, the PMA block is isolated from the rest
of the chip — ensuring optimal signal integrity. For the transceivers, you can use the channel PLL of an unused
receiver PMA as an additional transmit PLL.
Table 20: PMA Features of the Transceivers in Arria V Devices
Features
Backplane support
Chip-to-chip support
PLL-based clock recovery
Programmable serializer and
deserializer (SERDES)
Equalization and pre-emphasis
Ring oscillator transmit PLLs
Capability
? Arria V GX, GT, SX, and ST devices — Driving capability at
6.5536 Gbps with up to 25 dB channel loss
? Arria V GZ devices — Driving capability at 12.5 Gbps with up to 16 dB
channel loss
? Arria V GX, GT, SX, and ST devices — Up to 10.3125 Gbps
? Arria V GZ devices — Up to 12.5 Gbps
Superior jitter tolerance
Flexible SERDES width
? Arria V GX, GT, SX, and ST devices — Up to 14.37 dB of pre-emphasis
and up to 4.7 dB of equalization
? Arria V GZ devices — 4-tap pre-emphasis and de-emphasis
611 Mbps to 10.3125 Gbps
LC oscillator ATX transmit PLLs 600 Mbps to 12.5 Gbps
(Arria V GZ devices only)
Input reference clock range
27 MHz to 710 MHz
Transceiver dynamic reconfigura- Allows the reconfiguration of a single channel without affecting the
tion
operation of other channels
PCS Features
The Arria V core logic connects to the PCS through an 8, 10, 16, 20, 32, 40, 64, 66, or 67 bit interface,
depending on the transceiver data rate and protocol. Arria V devices contain PCS hard IP to support
PCIe Gen1, Gen2, and Gen3, GbE, Serial RapidIO (SRIO), GPON, and CPRI.
All other standard and proprietary protocols within the following speed ranges are also supported:
? 611 Mbps to 6.5536 Gbps — supported through the custom double-width mode (up to 6.5536 Gbps) and
custom single-width mode (up to 3.75 Gbps) of the transceiver PCS hard IP.
? 6.5536 Gbps to 10.3125 Gbps — supported through dedicated 80 or 64 bit interface that bypass the PCS
hard IP and connects the PMA directly to the core logic. In Arria V GZ, this is supported in the transceiver
PCS hard IP.
Arria V Device Overview
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