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| 型号： | DK-DEV-5AGXB3N/ES |
| 厂商： | Altera |
| 文件页数： | 4/39页 |
| 文件大小： | 0K |
| 描述： | ARRIA V DEVELOPMENT KIT |
| 标准包装： | 1 |
| 系列： | Arria V GX |
| 类型： | FPGA |
| 适用于相关产品： | Arria? V GX |
| 所含物品： | 板，线缆，文档，电源 |
| 其它名称： | 544-2743 |
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Summary of Arria V Features
Feature
Description
AV-51001
2013.12.26
FPGA General-purpose I/Os ? 1.6 Gbps LVDS receiver and transmitter
(GPIOs)
External Memory Interface
? 800 MHz/1.6 Gbps external memory interface
? On-chip termination (OCT)
? 3.3 V support (2)
Memory interfaces with low latency:
? Hard memory controller-up to 1.066 Gbps
? Soft memory controller-up to 1.6 Gbps
Low-power high-speed serial ? 600 Mbps to 12.5 Gbps integrated transceiver speed
interface
HPS
(Arria V SX and ST devices
only)
? Less than 105 mW per channel at 6 Gbps, less than 165 mW per channel at
10 Gbps, and less than 170 mW per channel at 12.5 Gbps
? Transmit pre-emphasis and receiver equalization
? Dynamic partial reconfiguration of individual channels
? Physical medium attachment (PMA) with soft PCS that supports 9.8304 Gbps
CPRI (Arria V GT and ST only)
? PMA with hard PCS that supports up to 9.8 Gbps CPRI (Arria V GZ only)
? Hard PCS that supports 10GBASE-R and 10GBASE-KR (Arria V GZ only)
? Dual-core ARM Cortex-A9 MPCore processor-up to 800 MHz maximum
frequency with support for symmetric and asymmetric multiprocessing
? Interface peripherals — 10/100/1000 Ethernet media access control (EMAC)
, USB 2.0 On-The-GO (OTG) controller, quad serial peripheral interface
(QSPI) flash controller, NAND flash controller, Secure Digital/MultiMedi-
aCard (SD/MMC) controller, UART, serial peripheral interface (SPI), I2C
interface, and up to 85 HPS GPIO interfaces
? System peripherals — general-purpose timers, watchdog timers, direct memory
access (DMA) controller, FPGA configuration manager, and clock and reset
managers
? On-chip RAM and boot ROM
? HPS – FPGA bridges — include the FPGA-to-HPS, HPS-to-FPGA, and
lightweight HPS-to-FPGA bridges that allow the FPGA fabric to issue
transactions to slaves in the HPS, and vice versa
? FPGA-to-HPS SDRAM controller subsystem — provides a configurable
interface to the multiport front end (MPFE) of the HPS SDRAM controller
? ARM CoreSight ? JTAG debug access port, trace port, and on-chip trace
storage
(2)
Arria V GZ devices support 3.3 V with a 3.0 V V CCIO .
Altera Corporation
Arria V Device Overview
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-DEV-5ASTD5N | 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件状态:在售 类型:FPGA 配套使用产品/相关产品:Arria? V ST 内容:板 标准包装:1 |
| DK-DEV-5CEA7N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5CEFA7F31C7N RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-5CEA7N/P | 制造商:Altera Corporation 功能描述:Cyclone VE Devkit Promotional 制造商:Altera 功能描述:Cyclone VE Devkit Promotional |
| DK-DEV-5CEA7NES | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5CEFA7F3 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-5CEA7NESP | 制造商:Altera Corporation 功能描述:KIT DEVELOPMENT CYCLONE V E |
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