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| 型号： | DK-DEV-5AGXB3N/ES |
| 厂商： | Altera |
| 文件页数： | 34/39页 |
| 文件大小： | 0K |
| 描述： | ARRIA V DEVELOPMENT KIT |
| 标准包装： | 1 |
| 系列： | Arria V GX |
| 类型： | FPGA |
| 适用于相关产品： | Arria? V GX |
| 所含物品： | 板，线缆，文档，电源 |
| 其它名称： | 544-2743 |
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34
Hardware and Software Development
AV-51001
2013.12.26
Related Information
Provides detailed information about power supply pin connection guidelines and power regulator sharing.
Provides detailed information about power supply pin connection guidelines and power regulator sharing.
Hardware and Software Development
For hardware development, you can configure the HPS and connect your soft logic in the FPGA fabric to
the HPS interfaces using the Qsys system integration tool in the Quartus II software.
For software development, the ARM-based SoC devices inherit the rich software development ecosystem
available for the ARM Cortex-A9 MPCore processor. The software development process for Altera SoCs
follows the same steps as those for other SoC devices from other manufacturers. Support for Linux, VxWorks ? ,
and other operating systems is available for the SoCs. For more information on the operating systems support
availability, contact the Altera sales team.
You can begin device-specific firmware and software development on the Altera SoC Virtual Target. The
Virtual Target is a fast PC-based functional simulation of a target development system — a model of a complete
development board that runs on a PC. The Virtual Target enables the development of device-specific
production software that can run unmodified on actual hardware.
Related Information
Dynamic and Partial Reconfiguration
The Arria V devices support dynamic reconfiguration and partial reconfiguration (19) .
Dynamic Reconfiguration
The dynamic reconfiguration feature allows you to dynamically change the transceiver data rates, PMA
settings, or protocols of a channel, without affecting data transfer on adjacent channels. This feature is ideal
for applications that require on-the-fly multiprotocol or multirate support. You can reconfigure the PMA,
PCS, and PCIe hard IP blocks with dynamic reconfiguration.
Partial Reconfiguration
Note: Partial reconfiguration is an advanced feature of the device family. If you are interested in using
partial reconfiguration, contact Altera for support.
Partial reconfiguration allows you to reconfigure part of the device while other sections of the device remain
operational. This capability is important in systems with critical uptime requirements because it allows you
to make updates or adjust functionality without disrupting services.
(19)
Partial reconfiguration is an advanced feature of the device family. If you are interested in using partial
reconfiguration, contact Altera for support.
Altera Corporation
Arria V Device Overview
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DK-DEV-5ASTD5N | 功能描述:KIT DEV ARRIA V FPGA 制造商:altera 系列:Arria V ST 零件状态:在售 类型:FPGA 配套使用产品/相关产品:Arria? V ST 内容:板 标准包装:1 |
| DK-DEV-5CEA7N | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5CEFA7F31C7N RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-5CEA7N/P | 制造商:Altera Corporation 功能描述:Cyclone VE Devkit Promotional 制造商:Altera 功能描述:Cyclone VE Devkit Promotional |
| DK-DEV-5CEA7NES | 功能描述:可编程逻辑 IC 开发工具 FPGA Development Kit For 5CEFA7F3 RoHS:否 制造商:Altera Corporation 产品:Development Kits 类型:FPGA 工具用于评估:5CEFA7F3 接口类型: 工作电源电压: |
| DK-DEV-5CEA7NESP | 制造商:Altera Corporation 功能描述:KIT DEVELOPMENT CYCLONE V E |
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