参数资料
型号: DS2152L+
厂商: Maxim Integrated Products
文件页数: 19/97页
文件大小: 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
功能: 单芯片收发器
接口: T1
电路数: 1
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 管件
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
产品目录页面: 1429 (CN2011-ZH PDF)
DS2152
26 of 97
CCR3: COMMON CONTROL REGISTER 3 (Address = 30 Hex)
(MSB)
(LSB)
ESMDM
ESR
RLOSF
RSMS
PDE
ECUS
TLOOP
SYMBOL
POSITION
NAME AND DESCRIPTION
ESMDM
CCR3.7
Elastic Store Minimum Delay Mode. See Section 11.3 for
details.
0 = elastic stores operate at full two-frame depth
1 = elastic stores operate at 32-bit depth
ESR
CCR3.6
Elastic Store Reset. Setting this bit from a 0 to a 1 will force the
elastic stores to a known depth. Should be toggled after
RSYSCLK and TSYSCLK have been applied and are stable.
Must be cleared and set again for a subsequent reset.
RLOSF
CCR3.5
Function of the RLOS/LOTC Output.
0 = Receive Loss of Sync (RLOS)
1 = Loss of Transmit Clock (LOTC)
RSMS
CCR3.4
RSYNC Multiframe Skip Control. Useful in framing format
conversions from D4 to ESF. This function is not available when
the receive side elastic store is enabled.
0 = RSYNC will output a pulse at every multiframe
1 = RSYNC will output a pulse at every other multiframe
Note: for this bit to have any affect, the RSYNC must be set to
output multiframe pulses (RCR2.4 = 1 and RCR2.3 = 0).
PDE
CCR3.3
Pulse Density Enforcer Enable.
0 = disable transmit pulse density enforcer
1 = enable transmit pulse density enforcer
ECUS
CCR3.2
Error Counter Update Select. See Section 6 for details.
0 = update error counters once a second
1 = update error counters every 42ms (333 frames)
TLOOP
CCR3.1
Transmit Loop Code Enable. See Section 13 for details.
0 = transmit data normally
1 = replace normal transmitted data with repeating code as
defined in TCD register
CCR3.0
Not Assigned. Must be set to 0 when written.
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