参数资料
型号: DS2152L+
厂商: Maxim Integrated Products
文件页数: 6/97页
文件大小: 0K
描述: IC TXRX T1 1CHIP ENHNCD 100-LQFP
产品培训模块: Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装: 90
功能: 单芯片收发器
接口: T1
电路数: 1
电源电压: 4.75 V ~ 5.25 V
电流 - 电源: 75mA
工作温度: 0°C ~ 70°C
安装类型: 表面贴装
封装/外壳: 100-LQFP
供应商设备封装: 100-LQFP(14x14)
包装: 管件
包括: DSX-1 和 CSU 线路补偿发生器,HDLC 控制器,带内回路代码发生器和检测器
产品目录页面: 1429 (CN2011-ZH PDF)
DS2152
14 of 97
2.4 Line Interface Pins
PIN
NAME
FUNCTION
21
MCLK
Master Clock Input. A 1.544MHz (±50ppm) clock source with TTL levels is applied at
this pin. This clock is used internally for both clock/data recovery and for jitter
attenuation. A quartz crystal of 1.544MHz may be applied across MCLK and XTALD
instead of the TTL level clock source.
22
XTALD
Quartz Crystal Driver. A quartz crystal of 1.544MHz may be applied across MCLK
and XTALD instead of a TTL level clock source at MCLK. Leave open circuited if a
TTL clock source is applied at MCLK.
13
8XCLK
Eight Times Clock. A 12.352MHz clock that is frequency locked to the 1.544MHz
clock provided from the clock/data recovery block (if the jitter attenuator is enabled on
the receive side) or from the TCLKI pin (if the jitter attenuator is enabled on the transmit
side). Can be internally disabled via the TEST2 register if not needed.
12
LIUC
Line Interface Connect. Tie low to separate the line interface circuitry from the
framer/formatter circuitry and activate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/
RCLKI pins. Tie high to connect the line interface circuitry to the framer/formatter
circuitry and deactivate the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins. When
LIUC is tied high, the TPOSI/TNEGI/TCLKI/RPOSI/RNEGI/RCLKI pins should be
tied low.
16, 17
RTIP,
RRING
Receive Tip and Ring. Analog inputs for clock recovery circuitry. These pins connect
via a 1:1 transformer to the T1 line. See Section 15 for details.
29, 32
TTIP,
TRING
Transmit Tip and Ring. Analog line driver outputs. These pins connect via a 1:1.15 or
1:1.36 step-up transformer to the T1 line. See Section 15 for details.
2.5 Supply Pins
PIN
NAME
FUNCTION
44, 61,
81, 83
DVDD
Digital Positive Supply. 5.0V ±5%. Should be tied to the RVDD and TVDD pins.
18
RVDD
Receive Analog Positive Supply. 5.0V ±5%. Should be tied to the DVDD and TVDD
pins.
31
TVDD
Transmit Analog Positive Supply. 5.0V ±5%. Should be tied to the RVDD and DVDD
pins.
45, 60,
80, 84
DVSS
Digital Signal Ground. Should be tied to the RVSS and TVSS pins.
19, 20,
24
RVSS
Receive Analog Signal Ground. 0V. Should be tied to the DVSS and TVSS pins.
30
TVSS
Transmit Analog Ground. 0V. Should be tied to the RVSS and DVSS pins.
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