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| 型号： | DS2152L+ |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 44/97页 |
| 文件大小： | 0K |
| 描述： | IC TXRX T1 1CHIP ENHNCD 100-LQFP |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 90 |
| 功能： | 单芯片收发器 |
| 接口： | T1 |
| 电路数： | 1 |
| 电源电压： | 4.75 V ~ 5.25 V |
| 电流 - 电源： | 75mA |
| 工作温度： | 0°C ~ 70°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 100-LQFP |
| 供应商设备封装： | 100-LQFP（14x14） |
| 包装： | 管件 |
| 包括： | DSX-1 和 CSU 线路补偿发生器，HDLC 控制器，带内回路代码发生器和检测器 |
| 产品目录页面： | 1429 (CN2011-ZH PDF) |
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DS2152
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8.2 Hardware-Based Signaling
8.2.1 Receive Side
In the receive side of the hardware based signaling, there are two operating modes for the signaling
buffer: signaling extraction and signaling reinsertion. Signaling extraction involves pulling the signaling
bits from the receive data stream and buffering them over a four multiframe buffer and outputting them in
a serial PCM fashion on a channel-by-channel basis at the RSIG output. This mode is always enabled. In
this mode, the receive elastic store may be enabled or disabled. If the receive elastic store is enabled, then
the backplane clock (RSYSCLK) can be either 1.544MHz or 2.048MHz. In the ESF framing mode, the
ABCD signaling bits are output on RSIG in the lower nibble of each channel. The RSIG data is updated
once a multiframe (3ms) unless a freeze is in effect. In the D4 framing mode, the AB signaling bits are
output twice on RSIG in the lower nibble of each channel. Hence, bits 5 and 6 contain the same data as
bits 7 and 8, respectively, in each channel. The RSIG data is updated once a multiframe (1.5ms) unless a
freeze is in effect. See the timing diagrams in Section 16 for some examples.
The other hardware-based signaling operating mode called signaling reinsertion can be invoked by setting
the RSRE control bit high (CCR4.7 = 1). In this mode, the user will provide a multiframe sync at the
RSYNC pin and the signaling data will be re-aligned at the RSER output according to this applied
multiframe boundary. In this mode, the elastic store must be enabled however the backplane clock can be
either 1.544MHz or 2.048MHz.
If the signaling reinsertion mode is enabled, the user can control which channels have signaling
reinsertion performed on a channel-by-channel basis by setting the RPCSI control bit high (CCR4.6) and
then programming the RCHBLK output pin to go high in the channels in which the signaling reinsertion
should not occur. If the RPCSI bit is set low, then signaling reinsertion will occur in all channels when
the signaling reinsertion mode is enabled (RSRE = 1). How to control the operation of the RCHBLK
output pin is covered in Section 10. In signaling reinsertion mode, the user has the option to replace all of
the extracted robbed-bit signaling bit positions with 1s. This option is enabled via the RFSA1 control bit
(CCR4.5) and it can be invoked on a per-channel basis by setting the RPCSI control bit (CCR4.6) high
and then programming RCHBLK appropriately just like the per-channel signaling reinsertion operates.
The signaling data in the four-multiframe buffer will be frozen in a known good state upon either a loss of
synchronization (OOF event), carrier loss, or frame slip. This action meets the requirements of BellCore
TR-TSY-000170 for signaling freezing. To allow this freeze action to occur, the RFE control bit
(CCR4.4) should be set high. The user can force a freeze by setting the RFF control bit (CCR4.3) high.
The RSIGF output pin provides a hardware indication that a freeze is in effect. The four-multiframe
buffer provides a three-multiframe delay in the signaling bits provided at the RSIG pin (and at the RSER
pin if RSRE = 1). When freezing is enabled (RFE = 1), the signaling data will be held in the last known
good state until the corrupting error condition subsides. When the error condition subsides, the signaling
data will be held in the old state for at least an additional 9ms (or 4.5ms in D4 framing mode) before
being allowed to be updated with new signaling data.
8.2.2 Transmit Side
Via the THSE control bit (CCR4.2), the DS2152 can be set up to take the signaling data presented at the
TSIG pin and insert the signaling data into the PCM data stream that is being input at the TSER pin. The
user can control which channels are to have signaling data from the TSIG pin inserted into them on a
channel-by-channel basis by setting the TPCSI control bit (CCR4.1) high. When TPCSI is enabled,
channels in which the TCHBLK output has been programmed to be set high in, will not have signaling
data from the TSIG pin inserted into them. The hardware signaling insertion capabilities of the DS2152
are available whether the transmit side elastic store is enabled or disabled. If the elastic store is enabled,
the backplane clock (TSYSCLK) can be either 1.544 MHz or 2.048 MHz.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS2152L+ | 功能描述:网络控制器与处理器 IC Enhanced T1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2152L-ES | 制造商:DALL 功能描述: |
| DS2152LN | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2152LN+ | 功能描述:网络控制器与处理器 IC RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS2153DK | 功能描述:KIT DESIGN TXRX E1 DS2153 RoHS:否 类别:编程器，开发系统 >> 过时/停产零件编号 系列:- 标准包装:1 系列:- 传感器类型:CMOS 成像，彩色（RGB） 传感范围:WVGA 接口:I²C 灵敏度:60 fps 电源电压:5.7 V ~ 6.3 V 嵌入式:否 已供物品:成像器板 已用 IC / 零件:KAC-00401 相关产品:4H2099-ND - SENSOR IMAGE WVGA COLOR 48-PQFP4H2094-ND - SENSOR IMAGE WVGA MONO 48-PQFP |
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