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| 型号： | DS21Q59DK |
| 厂商： | Maxim Integrated Products |
| 文件页数： | 56/76页 |
| 文件大小： | 0K |
| 描述： | KIT DESIGN FOR DS21Q59 |
| 产品培训模块： | Lead (SnPb) Finish for COTS Obsolescence Mitigation Program |
| 标准包装： | 1 |
| 主要目的： | 电信，调帧器和线路接口装置（LIU） |
| 已用 IC / 零件： | DS21Q59 |
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DS21Q59 Quad E1 Transceiver
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1. ACRONYMS
The following abbreviations are used throughout this data sheet:
FAS
Frame Alignment Signal
CAS
Channel Associated Signaling
MF
Multiframe
Si
International Bits
CRC4
Cyclical Redundancy Check
CCS
Common Channel Signaling
Sa
Additional bits
E-Bit
CRC4 Error Bits
LOC
Loss of Clock
TCLK
This generally refers to the transmit rate clock and can reference an actual input signal to the
device (TCLK) or an internally derived signal used for transmission.
RCLK
This generally refers to the recovered network clock and can be a reference to an actual output
signal from the device or an internal signal.
2. DETAILED DESCRIPTION
The LIU is composed of a transmit interface, receive interface, and a jitter attenuator. The transmit interface
generates the necessary waveshapes for driving the network, depending on the type of media used. E1 waveform
generation includes G.703 waveshapes for both 75
W coax and 120W twisted cables. The receive interface recovers
clock and data from the network. The receive sensitivity adjusts automatically to the incoming signal. The jitter
attenuator removes phase jitter from the transmitted or received signal. The crystal-less jitter attenuator only
requires a 2.048MHz MCLK and can be placed in either the transmit or receive data paths. An additional feature of
the LIU is a code mark inversion (CMI) coder/decoder for interfacing to optical networks.
On the transmit side, the backplane interface section provides clock/data and frame-sync signals to the framer. The
framer inserts the appropriate synchronization framing patterns, alarm information, calculates and inserts the CRC
codes, and provides the HDB3 (zero code suppression) and alternate mark inversion (AMI) line coding. The
receive-side framer decodes AMI and HDB3 line coding, synchronizes to the data stream, reports alarm
information, counts framing/coding/CRC errors, and provides clock/data and frame-sync signals to the backplane
interface section.
The backplane interface provides a versatile method of sending and receiving data from the host system. The
receive elastic store provides a method for interfacing to asynchronous systems. The elastic store also manages
slip conditions (asynchronous interface). An interleave bus option (IBO) is provided to allow multiple E1 lines to
share a high-speed backplane.
The parallel port provides access for control and configuration of all the DS21Q59’s features. Diagnostic
capabilities include loopbacks, PRBS pattern generation/detection, and 16-bit loop-up and loop-down code
generation and detection. The device fully meets all the latest E1 specifications, including ITU-T G.703, G.704,
G.706, G.823, G.732 and I.431 ETS 300 011, ETS 300 233, and ETS 300 166 as well as CTR12 and CTR4.
The DS21Q59 is optimized for high-density termination of E1 lines. Two significant features are included for this
type of application: the IBO and a system clock synthesizer feature. The IBO allows up to eight E1 data streams to
be multiplexed onto a single high-speed PCM bus without additional external logic. The system clock synthesizer
allows any of the E1 lines to be selected as the master source of the clock for the system and for all the
transmitters. This is also accomplished without the need of external logic. Each of the four transceivers has a clock
and data jitter attenuator that can be assigned to either the transmit or receive path. In addition there is a single,
undedicated clock jitter attenuator that can be hardware configured as needed by the user. Each transceiver also
contains a PRBS pattern generator and detector. Figure 23-1 shows a simplified typical application that terminates
eight E1 lines (transmit and receive pairs) and combines the data into a single 16.384MHz PCM bus. The
16.384MHz system clock is derived and phase-locked to one of the eight E1 lines. On the receive side of each port,
an elastic store provides logical management of any slip conditions due to the asynchronous relationship of the
eight E1 lines. In this application all eight transmitters are timed to the selected E1 line.
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相关代理商/技术参数 |
参数描述 |
|---|---|
| DS21Q59L | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59L+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59LN | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21Q59LN+ | 功能描述:网络控制器与处理器 IC Quad E1 Transceiver RoHS:否 制造商:Micrel 产品:Controller Area Network (CAN) 收发器数量: 数据速率: 电源电流（最大值）:595 mA 最大工作温度:+ 85 C 安装风格:SMD/SMT 封装 / 箱体:PBGA-400 封装:Tray |
| DS21S07A | 制造商:Maxim Integrated Products 功能描述: |
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