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参数资料
型号： DS33ZH11+
厂商： Maxim Integrated Products
文件页数： 87/172页
文件大小： 0K
描述： IC MAPPER ETHERNET 100CSBGA
产品培训模块： Lead (SnPb) Finish for COTS
Obsolescence Mitigation Program
标准包装： 7
应用： 数据传输
接口： 串行
电源电压： 1.8V，2.5V，3.3V
封装/外壳： 100-LFBGA，CSPBGA
供应商设备封装： 100-CSBGA（10x10）
包装： 托盘
安装类型： 表面贴装
DS33Z11 Ethernet Mapper
21 of 172
NAME
PIN #
DS33Z11
CSBGA
(169)
PIN #
DS33ZH1
1
BGA(100)
TYPE
FUNCTION
A2/X86ED
A2
Potential
future
revision to
add on
ball B4
—
Address Bit 2: Address bit 2 of the microprocessor
interface.
X86ED (Hardware Mode): When in Hardware Mode,
setting this pin high enables X.86 encapsulation for both
the transmit and receive data. When 0, HDLC
encapsulation is used. The register used to control this
function in Software Mode is LI.TX86EDE.
A3
B2
—
Address Bit 3: Address bit 3 of the microprocessor
interface.
A4
C2
—
Address Bit 4: Address bit 4 of the microprocessor
interface.
A5
A3
—
Address Bit 5: Address bit 5 of the microprocessor
interface.
A6
B3
—
Address Bit 6: Address bit 6 of the microprocessor
interface.
A7
C3
—
Address Bit 7: Address bit 7 of the microprocessor
interface.
A8
A4
—
Address Bit 8: Address bit 8 of the microprocessor
interface.
A9
B4
—
Address Bit 9: Address bit 9 of the microprocessor
interface. Most Significant Bit.
D0/MOSI
A5
E8
IOZ
Data Bit 0: Bi-directional data bit 0 of the microprocessor
interface. Least Significant Bit. Not driven when
CS = 1 or
RST = 0.
Master Out Slave In (SPI Mode): Data stream that
provides the instruction and address information to the
external EEPROM when in SPI Master Mode. MOSI is
updated on the rising edge when CKPHA is set high, and
on the falling edge when set low.
D1/MISO
A6
E9
IOZ
Data Bit 1: Bidirectional data bit 1 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
Master In Slave Out (SPI Mode): Data path from the SPI
EEPROM to the DS33Z11. Must be synchronous with
SPICK. The Serial EEPROM SPI Interface will provide
data to the DS33Z11, MSB first. MISO is sampled on the
falling edge when CKPHA is set high, and on the rising
edge when set low.
D2/SPICK
A7
E10
IOZ
Data Bit 2: Bidirectional data bit 2 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
SPICK: Provides clocking for SPI transactions.
D3
B5
—
IOZ
Data Bit 3: Bidirectional data bit 3 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
D4
B6
—
IOZ
Data Bit 4: Bidirectional data bit 4 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
D5
B7
—
IOZ
Data Bit 5: Bidirectional data bit 5 of the microprocessor
interface. Not driven when
CS = 1 or RST = 0.
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