- 您现在的位置：买卖IC网 > PDF目录1917 > DSP56303VL100B1 (Freescale Semiconductor)IC DSP 24BIT 100MHZ 196-BGA PDF资料下载
参数资料
| 型号： | DSP56303VL100B1 |
| 厂商： | Freescale Semiconductor |
| 文件页数： | 32/108页 |
| 文件大小： | 0K |
| 描述： | IC DSP 24BIT 100MHZ 196-BGA |
| 标准包装： | 630 |
| 系列： | DSP563xx |
| 类型： | 定点 |
| 接口： | 主机接口，SSI，SCI |
| 时钟速率： | 100MHz |
| 非易失内存： | ROM（576 B） |
| 芯片上RAM： | 24kB |
| 电压 - 输入/输出： | 3.30V |
| 电压 - 核心： | 3.30V |
| 工作温度： | -40°C ~ 100°C |
| 安装类型： | 表面贴装 |
| 封装/外壳： | 196-LBGA |
| 供应商设备封装： | 196-MAPBGA（15x15） |
| 包装： | 托盘 |
第1页第2页第3页第4页第5页第6页第7页第8页第9页第10页第11页第12页第13页第14页第15页第16页第17页第18页第19页第20页第21页第22页第23页第24页第25页第26页第27页第28页第29页第30页第31页当前第32页第33页第34页第35页第36页第37页第38页第39页第40页第41页第42页第43页第44页第45页第46页第47页第48页第49页第50页第51页第52页第53页第54页第55页第56页第57页第58页第59页第60页第61页第62页第63页第64页第65页第66页第67页第68页第69页第70页第71页第72页第73页第74页第75页第76页第77页第78页第79页第80页第81页第82页第83页第84页第85页第86页第87页第88页第89页第90页第91页第92页第93页第94页第95页第96页第97页第98页第99页第100页第101页第102页第103页第104页第105页第106页第107页第108页
DSP56303 Technical Data, Rev. 11
Freescale Semiconductor
iii
Features
Table 1 lists the features of the DSP56303 device.
Table 1. DSP56303 Features
Feature
Description
High-Performance
DSP56300 Core
100 million multiply-accumulates per second (MMACS) with a 100 MHz clock at 3.3 V nominal
Object code compatible with the DSP56000 core with highly parallel instruction set
Data arithmetic logic unit (Data ALU) with fully pipelined 24
× 24-bit parallel multiplier-accumulator (MAC),
56-bit parallel barrel shifter (fast shift and normalization; bit stream generation and parsing), conditional
ALU instructions, and 24-bit or 16-bit arithmetic support under software control
Program control unit (PCU) with position-independent code (PIC) support, addressing modes optimized for
DSP applications (including immediate offsets), internal instruction cache controller, internal memory-
expandable hardware stack, nested hardware DO loops, and fast auto-return interrupts
Direct memory access (DMA) with six DMA channels supporting internal and external accesses; one-, two-
, and three-dimensional transfers (including circular buffering); end-of-block-transfer interrupts; and
triggering from interrupt lines and all peripherals
Phase-lock loop (PLL) allows change of low-power divide factor (DF) without loss of lock and output clock
with skew elimination
Hardware debugging support including on-chip emulation (OnCE‘) module, Joint Test Action Group (JTAG)
test access port (TAP)
Internal Peripherals
Enhanced 8-bit parallel host interface (HI08) supports a variety of buses (for example, ISA) and provides
glueless connection to a number of industry-standard microcomputers, microprocessors, and DSPs
Two enhanced synchronous serial interfaces (ESSI), each with one receiver and three transmitters (allows
six-channel home theater)
Serial communications interface (SCI) with baud rate generator
Triple timer module
Up to thirty-four programmable general-purpose input/output (GPIO) pins, depending on which peripherals
are enabled
Internal Memories
192
× 24-bit bootstrap ROM
8 K
× 24-bit RAM total
Program RAM, instruction cache, X data RAM, and Y data RAM sizes are programmable:
External Memory
Expansion
Data memory expansion to two 256 K
× 24-bit word memory spaces using the standard external address
lines
Program memory expansion to one 256 K
× 24-bit words memory space using the standard external
address lines
External memory expansion port
Chip select logic for glueless interface to static random access memory (SRAMs)
Internal DRAM Controller for glueless interface to dynamic random access memory (DRAMs)
Power Dissipation
Very low-power CMOS design
Wait and Stop low-power standby modes
Fully static design specified to operate down to 0 Hz (dc)
Optimized power management circuitry (instruction-dependent, peripheral-dependent, and mode-
dependent)
Packaging
144-pin TQFP package in lead-free or lead-bearing versions
196-pin molded array plastic-ball grid array (MAP-BGA) package in lead-free or lead-bearing versions
Program RAM
Size
Instruction
Cache Size
X Data RAM
Size
Y Data RAM
Size
Instruction
Cache
Switch Mode
4096
× 24-bit
0
2048
× 24-bit
2048
× 24-bit
disabled
3072
× 24-bit
1024
× 24-bit
2048
× 24-bit
2048
× 24-bit
enabled
disabled
2048
× 24-bit
0
3072
× 24-bit
3072
× 24-bit
disabled
enabled
1024
× 24-bit
1024
× 24-bit
3072
× 24-bit
3072
× 24-bit
enabled
相关PDF资料 |
PDF描述 |
|---|---|
| DSP56311VF150B1 | IC DSP 24BIT 150MHZ 196-BGA |
| DSP56321VF200R2 | IC DSP 24BIT 200MHZ 196-BGA |
| DSP56852VFE | IC DSP 16BIT 120MHZ 81-MAPBGA |
| DSP56854FGE | IC DSP 16BIT 120MHZ 128-LQFP |
| DSP56855BUE | IC DSP 16BIT 120MHZ 100-LQFP |
相关代理商/技术参数 |
参数描述 |
|---|---|
| DSP56304GC66 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:24-Bit Digital Signal Processor |
| DSP56304GC80 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:24-Bit Digital Signal Processor |
| DSP56304PV66 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:24-Bit Digital Signal Processor |
| DSP56304PV80 | 制造商:未知厂家 制造商全称:未知厂家 功能描述:24-Bit Digital Signal Processor |
| DSP56305DS | 制造商:未知厂家 制造商全称:未知厂家 功能描述:DSP56305 Single Chip Channel Codec Digital Signal Processor Data Sheet |
发布紧急采购，3分钟左右您将得到回复。