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参数资料
| 型号： | E28F200B5B60 |
| 厂商： | INTEL CORP |
| 元件分类： | PROM |
| 英文描述： | DIRECTIONAL COUPLER, 20DB, SMT |
| 中文描述： | 256K X 8 FLASH 5V PROM, 70 ns, PDSO48 |
| 封装： | 12 X 20 MM, TSOP-48 |
| 文件页数： | 32/44页 |
| 文件大小： | 345K |
| 代理商： | E28F200B5B60 |
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28F200B5, 28F004/400B5, 28F800B5
E
38
PRELIMINARY
5.10
AC Characteristics—Write Operations—Commercial and Extended
Temperature
Comm
Extended
#
Sym
Parameter
Note
Min
Max
Min
Max
Unit
W1
tPHWL (tPHEL)
RP# High Recovery to WE# (CE#) Going
Low
450
ns
W2
tELWL (tWLEL)
CE# (WE#) Setup to WE# (CE#) Going
Low
00
ns
W3
tWP
Write Pulse Width
9
50
60
ns
W4
tDVWH (tDVEH)
Data Setup to WE# (CE#) Going High
4
50
60
ns
W5
tAVWH (tAVEH)
Address Setup to WE# (CE#) Going High
3
50
60
ns
W6
tWHEH (tEHWH)
CE# (WE#) Hold from WE# (CE#) High
0
ns
W7
tWHDX (tEHDX)
Data Hold from WE# (CE#) High
4
0
ns
W8
tWHAX (tEHAX)
Address Hold from WE# (CE#) High
3
0
ns
W9
tWPH
Write Pulse Width High
VCC = 5 V
± 5%
10
ns
VCC = 5 V
±
10%
20
ns
W10 tPHHWH (tPHHEH)
RP# VHH Setup to WE# (CE#) Going High
6,8
100
ns
W11 tVPWH (tVPEH)VPP Setup to WE# (CE#) Going High
5,8
100
ns
W12 tQVPH
RP# VHH Hold from Valid SRD
6,8
0
ns
W13 tQVVL
VPP Hold from Valid SRD
5,8
0
ns
W14 tPHBR
Boot Block Lock Delay
7,8
100
ns
NOTES:
1. Read timing characteristics during program and erase operations are the same as during read-only operations. Refer to
AC
Characteristics—Read-Only Operations.
2. The on-chip WSM completely automates program/erase operations; program/erase algorithms are now controlled internally
which includes verify operations.
3. Refer to command definition table for valid A
IN. (Table 7)
4. Refer to command definition table for valid D
IN. (Table 7)
5. Program/erase durations are measured to valid SRD data (successful operation, SR.7 = 1).
6. For boot block program/erase, RP# should be held at V
HH or WP# should be held at VIH until operation completes
successfully.
7. Time t
PHBR is required for successful locking of the boot block.
8. Sampled, but not 100% tested.
9. Write pulse width (tWP) is defined from CE# or WE# going low (whichever goes low last) to CE# or WE# going high
(whichever goes high first). Hence, tWP = tWLWH = tELEH = tWLEH = tELWH.
10. Write pulse width high (tWPH) is defined from CE# or WE# going high (whichever goes high first)to CE# or WE# going low
(whichever goes low first). Hence, tWPH = tWHWL = tEHEL = tWHEL = tEHWL.
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相关代理商/技术参数 |
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| E28F200B5B80 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| E28F200B5T60 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:SMART 5 BOOT BLOCK FLASH MEMORY FAMILY 2, 4, 8 MBIT |
| E28F200B5T80 | 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Intel 功能描述: |
| E28F200BL-B150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
| E28F200BL-T150 | 制造商:INTEL 制造商全称:Intel Corporation 功能描述:2-MBIT (128K x 16, 256K x 8)LOW-POWER BOOT BLOCK FLASH MEMORY FAMILY |
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