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| 型号： | EM6640SO18B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 微控制器 |
| 文件页数： | 19/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18B |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
26
www.emmicroelectronic.com
7.3 Event Counting
The counter can be used in a special event count mode where a certain number of events (clocks) on the PA[0] or
PA[3] input are counted. In this mode the counting will start directly on the next active clock edge as selected on
the PortA input configuration. Internally the active clock edge is always the positive edge.
The Event Count Mode is switched on by setting bit EvCount in the register RegCCntl2 to ‘1’.
PA[3] and PA[0] inputs can be inverted depending on register OPTIntEdgPA but should be debounced. The
debouncer is switched on in register OPTDebIntPA bits NoDebIntPA[3]=0 and NoDebIntPA[0]=0 its frequency
depends on the bit DebSel from register RegPresc setting. The inversion of the internal clock signal derived from
PA[3] or PA[0] is active with IntEdgPA[3] respectively IntEdgPA[0] equal to 1.
Figure 19. Internal clock synchronization
7.4 Compare Function
A previously loaded register value (Creg[9:0]) can be compared against the actual counter value (Count[9:0]). If
the two are matching (equality) then a interrupt (IRQComp) is generated. The compare function is switched on
with the bit EnComp in the register RegCCntl2. With EnComp = 0 never an IRQComp is generated. Starting the
counter with the same value as the compare register is possible, no IRQ is generated. The compare value must
be different from hex 0 in up-count mode and different from hex 3FF (resp. FF, 3F, F if limited bit counting) in
down-count mode. Full or Limited bit compare are possible, defined by bit SelIntComp in register RegSysCntl1.
The bit EnComp is reset with every load operation (Load = 1).
Full bit compare function.
To be in this mode, set the bit SelIntComp to ‘1’. The function behaves as described above independent of the
selected counter length. Limited bit counting together with full bit compare can be used to generate a certain
amount of IRQCount0 interrupts until the counter generates the IRQComp interrupt. With PWMOn=‘1’ the counter
would have automatically stopped after the IRQComp, with PWMOn=‘0’ it will continue until the software stops it.
Be careful, PWMOn also redefines the PortB PB[3] output data. (refer to section 7.5).
Limited bit compare
This is the default, with the bit SelIntComp set to ‘0’ the compare function will only take as many bits into account
as defined by the counter length (BitSel[1:0]) selection (see chapter 7.1).
7.5 Pulse Width Modulation (PWM) Generation
The PWM generator uses the behavior of the Compare function so EnComp must be set to activate the PWM
function. At each Roll Over or Compare Match the PWM state - which is output on PortB PB[3] - will toggle. The
start value on PB[3] is depending on the Up/DownCount Mode.
Setting PWMOn to ‘1’ in register RegPresc routes the counter PWM output to PortB PB[3]. Insure that PB[3] is
set to Output mode (refer to section 6.4 for the PortB setup). After using the PWM function, do not forget to reset
the bit PWMOn in order to have PB[3] in a normal mode.
The PWM signal generation is independent of the limited or full bit compare selection bit SelIntComp. However if
SelIntComp=1 (FULL) and the Counter Compare Function is limited to lower than 10 bits one can generate a
predefined number of output pulses. In this case, the number of output pulses is defined with the unused counter
bits. It will count from the start value until the IRQComp match.
ck
Start
Count[9:0
]
+ / - 1
EvCount = 0
ck
Start
Count[9:0
]
EvCount = 0
ck
Start
Count[9:0
]
EvCount = 1
ck
Start
Count[9:0
]
EvCount = 1
ck=counting clock frequency
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