参数资料
型号: EM6640SO18B
英文描述: Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN
中文描述: 微控制器
文件页数: 25/62页
文件大小: 620K
代理商: EM6640SO18B
EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
31
www.emmicroelectronic.com
The Serial Write Buffer
has two possible working modes :
8.1 SWB Automatic send mode
In this mode, one has first to prepare data to be sent (up to 256 bits), select the clock and write the bit SWBAuto
in RegSWBSizeH register. Then, executing HALT instruction starts the sending operation. During automatic
sending, one can not do anything with the microcontroller (instructions can not be executed because
of STANDBY mode). At the end of transmission, EM6640 comes out of STANDBY mode and generates a high
level on TestVar[3] meaning “transmission finished“.
This mode has additional features compared to interactive mode. In order to be fully flexible, one can decide to
send for the last package a number of clocks not egal to 4. The number goes from 1 to 4 clocks depending on bit
DiscCk[1:0] in register RegSWBCntl2. All four data bits are always transmitted independent of the number of
clocks selected.
The level of the last bit of the last package is automatically latched as long as the SWB is enabled.
Figure 23 represents two ends of transmission in automatic mode: 1st with data=b1010 and 2nd with data=0010
for the last nibble. Bit DiscCk[0] and bit DiscCk[1] are set to ‘1’, so only one SWBclock will be send for the last
package.
Figure 23 exemple of 2 ends of transmission (SysClk is shown two times longer for a better visibility)
S ysC lk
C k 15 0k H z
Ha lt
SW B d a t a
SW Bd a ta
la s t nibb le
SW B c lo c k
0
1
01
0
10
0
1
0
1
01
0
10
0
1
LS B
MS B
la s t d a ta =b10 10
SW B c lo c k
la s t data = b 001 0
8.1.1 SWB Automatic with external clock
In automatic mode, setting SWBFSel0 and SWBFSel1 to ‘0’ in register RegSWBCntl, selects an external clock
from the PA[0] input which can be used as a serial transmission clock. Serial clock and serial data will go out at
the same frequency as the clock provided on the PA[0] input. Depending of the value of CkExtDiv[1:0] bits in
register RegSWBCntl, the external clock applied on PA[0] can be divided internally by 1 (default), 4, 88 or 352
times.
The PA[0] input can be inverted depending on the register OPTIntEdgPA and debounced depending on the
register OPTDebIntPA. Refer to chapter IRQ on portA, page 16.
For external clock/1 selection, the transmission will start on the third positive clock edge or on the second
negative clock edge applied on PA[0], following the HALT command. This is depending of the PA[0] input
configuration, positive edge for the first case and negative edge for the second case.
For external clock/4, external clock/88 and external clock/352 selection, the transmission will start on the half
clock edge selection + 2 clocks (resp. 4th external clock, 46th external clock and 178 external clock) following the
HALT command.
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