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| 型号： | EM6640SO18B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 微控制器 |
| 文件页数： | 21/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18B |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
28
www.emmicroelectronic.com
In down count mode an interrupt request IRQCount0 is generated when the counter reaches 0. In up count
mode, an interrupt request is generated when the counter reaches 3FF (resp. FF,3F,F if limited bit counting).
Never an interrupt request is generated by loading a value into the counter register.
When the counter is programmed from Up into Down mode or vice versa, the counter value Count[9:0] gets
inverted. As a consequence, the initial value of the counter must be programmed after the Up/Down selection.
Loading the counter with hex 000 is equivalent to writing Stop mode, the Start bit is reset, no interrupt request is
generated.
How to use the counter;
1st, set the counter into stop mode (Start=0).
2nd, select the frequency and Up- or Down mode in RegCCntl1.
3rd, write the data registers RegCDataL, RegCDataM, RegCDataH (Counter start value and length)
4th, load the counter, Load=1, and choose the mode. (EvCount, PWM )
5th, if compare mode desired , then write RegCDataL, RegCDataM, RegCDataH (compare value)
6th, set bit Start and EnComp in RegCCntl2
7.7 10-bit Counter Registers
Table 7.7.1 register RegCCntl1
Bit
Name
Reset
R/W
Description
3
Up/Down
0
R/W
up or down counting
2
CountFSel2
0
R/W
input clock selection
1
CountFSel1
0
R/W
input clock selection
0
CountFsel0
0
R/W
input clock selection
Default : PA0 ,selected as input clock, Down counting
Table 7.7.2 Counter input frequency selection with CountFSel[2..0]
CountFSel2
CountFSel1
CountFSel0
clock source selection
0
Port A
PA[0]
0
1
Prescaler ck[19]
0
1
0
Prescaler ck[16]
0
1
Prescaler ck[13]
1
0
Prescaler ck[10]
1
0
1
Prescaler ck[4]
1
0
Prescaler ck[1]
1
Port A
PA[3]
Table 7.7.3 register RegCCntl2
Bit
Name
Reset
R/W
Description
3
Start
0
R/W
Start/Stop control
2
EvCount
0
R/W
event counter enable
1
EnComp
0
R/W
enable comparator
0
Load
0
R/W
Write: load counter register
Read: always 0
Default : Stop, No event count, no comparator, no load
Table 7.7.4 register RegSysCntl1
Bit
Name
Reset
R/W
Description
3
IntEn
0
R/W
general interrupt enable
2
SLEEP
0
R/W
Sleep mode
1
SelIntComp
0
R/W
compare Interrupt select
0
ChTmDis
0
R/W
for EM Test only
Default : interrupt on limited bit compare
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