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| 型号： | EM6640SO18B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 微控制器 |
| 文件页数： | 20/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18B |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
27
www.emmicroelectronic.com
For instance, loading the counter in UpCount mode with hex 000 and the comparator with hex C52 which will be
identified as :
- bits [11:10] are limiting the counter to limits to 4 bits length,
(BitSel[1,0])
- bits [9:4] are the unused counter bits = 05,
(nbr of PWM pulses)
- bits [3:0] (comparator value = 2).
(length of PWM pulse)
Thus after 5 PWM-pulses of 2 clocks cycles length the Counter generates an IRQComp and stops.
The same example with SelIntComp=0 (limited bit compare) will produce an unlimited nbr of 2 cycles PWM
pulses.
7.5.1 How the PWM generator works.
For UpCount Mode; Setting the counter in UpCount and PWM mode, the PB[3] PWM output is defined to be 0.
Each Roll Over will set the output to ‘1’ and each Compare Match will set it back to ‘0’. The Compare Match for
PWM always only works on the defined counter length. This, independent of the SelIntComp setting which is
valid only for the IRQ generation.
In above example the PWM starts with ‘0’ (UpCount),
2 cycles later Compare Match -> PWM to ‘0’,
14 cycles later RollOver -> PWM to ‘1’
2 cycles later Compare Match -> PWM to ‘0’ , etc. until the completion of the 5 pulses.
The normal IRQ generation remains on during PWM output. If no IRQ’s are wanted, the corresponding masks
need to be set.
In DownCount Mode everything is inverted. The PWM output starts with the ‘1’ value. Each Roll Over will set the
output to ‘0’ and each Compare Match will set it back to ‘1’.
7.5.2 PWM characteristics
PWM resolution is
: 10bits (1024 steps), 8bits (256 steps), 6bits (64 steps) or 4 bits (16 steps)
the minimal signal period is
: 16 (4-bit) x Fmax*
-> 16 x 1/ck[19]
-> 53 s
(600kHz)
the maximum signal period is
: 1024 x Fmin*
-> 1024 x 1/ck[1]
-> 1024 s
(600kHz)
the minimal pulse width is
: 1 bit
-> 1 x 1/ck[19]
-> 3.3s
(600kHz)
* This values are for Fmax or Fmin derived from the internal system clock (600kHz). Much shorter (and longer)
PWM pulses can be achieved by using the PortA as frequency input (undebounced input).
7.6 Counter setup
RegCDataL[3:0], RegCDataM[3:0], RegCDataH[1:0] are used to store the initial count value called CReg[9:0]
which is written into the count register bits Count[9:0] with the Load command. Load is automatically reset
thereafter. The counter value Count[9:0] can be read out at any time - except when using nondebounced high
frequency PortA input - but to maintain data integrity the lower nibble Count[3:0] must always be read first. The
ShCount[9:4] values are shadow registers to the counter. To keep the data integrity during a counter read
operation (3 reads), the counter values [9:4] are copied into these registers with the read of the count[3:0] register.
If using nondebounced high frequency PortA input the counter must be stopped while reading the Count[3:0]
value to maintain the data integrity.
Figure 20. PWM Output in UpCount Mode
data+1
data-1
data+2
data
...
001
000
3FE
3FF
clock
Count[9:0]
IRQCount0
IRQComp
PWMOutput
roll-over
compare
Figure 21. PWM Output in DownCount Mode
data-1
data+1
data-2
data
...
3FE
3FF
001
000
clock
Count[9:0]
IRQCount0
IRQComp
PWMOutput
roll-over
compare
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