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| 型号： | EM6640SO18B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 微控制器 |
| 文件页数： | 8/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18B |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
16
www.emmicroelectronic.com
6.2 PortA
The EM6640 has one four bit general purpose CMOS input port. The PortA input can be read at any time, pull-up
or pull-down resistors can be chosen by metal mask. All selections concerning PortA are bitwise executable. I.e.
Pull-up on PA[2], pull-down on PA[0], positive IRQ edge on PA[0] but negative on PA[1], etc.
In SLEEP mode the PortA inputs are continuously monitored to match the input reset condition which will
immediately wake the EM6640 from SLEEP mode. The pull-up or pull-down resistors remain active as defined in
the option register.
Figure 14. Input PortA configuration
IntEdgPA[n]=0
NoDebIntPA[n]=1
Mask opt
MPAPU[n]
IRQPA[3:0]
PA[n]terminal
PA0, PA3
for 10-bit
Counter
Mask opt
MPAPD[n]
Debouncer
(for port A)
P TestVAR
ck[8]
ck[17]
NoPull[n]
VBAT
(VDD
)
VSS
DB[3:0]
Input
combinations
Analog
debouncer
Sleep
control
SWB CkExt
6.2.1 IRQ on portA
For interrupt request generation (IRQ) one can choose direct or debounced input and positive or negative edge
IRQ triggering. With the debouncer selected ( OPtDebIntPA ) the input must be stable for two rising edges of the
selected debouncer clock ck[8] (default) or ck[17] (RegPresc), this means a worst case of 14mS (default) or 27
s
with a system clock of 600kHz.
Either a positive or a negative edge on the PortA inputs - after debouncer or not - can generate an interrupt
request. This selection is done in the option register OPTIntEdgPA.
All four bits of PortA can provide an IRQ, each pin with its own interrupt mask bit in the RegIRQMask1 register.
When an IRQ occurs, inspection of the RegIRQ1, RegIRQ2 and RegIRQ3 registers allow the interrupt to be
identified and treated.
At power on or after any reset the RegIRQMask1 is set to 0, thus disabling any input interrupt. A new interrupt is
only stored with the next active edge after the corresponding interrupt mask is cleared. See also the interrupt
chapter 10.
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