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参数资料
| 型号： | EM6640SO18B |
| 英文描述： | Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN |
| 中文描述： | 微控制器 |
| 文件页数： | 45/62页 |
| 文件大小： | 620K |
| 代理商： | EM6640SO18B |
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EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
5
www.emmicroelectronic.com
2.1 ACTIVE Mode
The active mode is the actual CPU running mode. Instructions are read from the internal ROM and executed by
the CPU. Go into standby mode via the halt instruction or go into sleep mode by writing the sleep bit.
2.2 STANDBY Mode
Executing a HALT instruction puts the EM6640 into
STANDBY mode. The voltage regulator, oscillator,
watchdog timer, interrupts and timers/counters are
operating. However, the CPU stops since the clock
related to instruction execution stops. Registers,
RAM and I/O pins retain their states prior to
STANDBY mode. STANDBY is canceled by a
RESET or an Interrupt request if enabled.
2.3 SLEEP Mode
Writing the Sleep bit in the RegSysCntl1 register
puts the EM6640 in SLEEP mode. The oscillator
stops and most functions of the EM6640 are
inactive. To be able to write the Sleep bit, the
SleepEn bit in RegSysCntl2 must first be set to "1".
In SLEEP mode only the voltage regulator is active.
The RAM data integrity is maintained. SLEEP mode
may be canceled only by the Input Reset from PortA
or the Sleep Counter Reset
.
During SLEEP mode and the following start up the EM6640 is in reset state. Waking up from SLEEP mode clears
the Sleep flag but not the SleepEn bit. Inspecting the SleepEn allows to determine if the EM6640 was powered
up (SleepEn = "0") or woken up from SLEEP mode (SleepEn = "1").
The bit NoInputRes in option register OptPaRst is inhibited is sleep mode.
TAKE CARE !!! To quit SLEEP mode, one must be sure to have a suitable defined combination of PortA inputs
for reset (see section 4.3).
Table 2.3.1 shows the state of the EM6640 functions in STANDBY and SLEEP modes
FUNCTION
STANDBY
SLEEP
Oscillator
Active
Stopped
Oscillator Watchdog
Active
Stopped
Instruction Execution
Stopped
Interrupt Functions
Active
Stopped
Registers and Flags
Retained
Reset
EEPROM
Retained
RAM data
Retained
Option Registers
Retained
Timer/Counter's
Active
Reset
Logic Watchdog
Active
Reset
Input PortA
Active
NoInputRes = "0"
Active
NoInputRes = "x"
I/O Port B
Active
High Impedance, no pulls
I/O Port C
Active
High Impedance, no pulls
SCR
Stopped
Active if enable
SWB
Active
Stopped
Voltage Level Detector
finishes on going measure, then stop
Stopped
3. Power Supply
The EM6640 is supplied by a single external power supply between VDD (VBat) and VSS (GND). A built-in
voltage regulator generates VregLogic providing regulated voltage for the oscillator and the internal logic. An
external capacitor (CVreg) has to be put on Vreg terminal (see Standard Operating Conditions, on page 55).
Vreg terminal is not intended to be used with external load except CVreg.
Figure 4 Mode transition diagram
ACTIVE
HALT
Instruction
SLEEP bit
write
IRQ
STANDBY
SLEEP
RESET=1
RESET=0
RESET=1
RESET
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