参数资料
型号: EM6640SO18B
英文描述: Advanced Synchronous Rectified Buck MOSFET Drivers with Pre-POR OVP; Temperature Range: -40°C to 85°C; Package: 10-DFN
中文描述: 微控制器
文件页数: 27/62页
文件大小: 620K
代理商: EM6640SO18B
EM6640
03/02 REV. C/446
Copyright
2002, EM Microelectronic-Marin SA
33
www.emmicroelectronic.com
8.2 SWB Interactive send mode
In interactive send mode, data to be sent must be loaded in RegSWBuff register (no RAM space is used for serial
transmission).
8.2.1 How the SWB in interactive mode works
One has first to select the serial transmission clock in RegSWBCntl register and load the first 4-bit package to be
sent in RegSWBuff register.
Then setting to “1“ the bit SWBStart in RegSWBSizeH register starts the transmission : data are transferred
from RegSWBuff register to shift register and put on serial data output. When RegSWBuff register is empty, an
interrupt request SWBempty which can not be masked is generated and TestVar[3] goes high.
According to the selected clock, one has to take into account how many instructions are needed to process
SWBempty interrupt request : recognize this interrupt (conditional jump on TESTvar[3]) and load the new 4-bit
package in RegSWBuff register.
Indeed, If processing of SWBempty interrupt request is too long and internal SHIFT register is empty before new
4-bit package was written in RegSWBuff register, the transmission is broken : serial clock output stops at "0", bit
SWBStart and SWBempty are cleared to “0“ and TestVar[3] remains to “1“. This could be the case for a 150kHz
transmission speed. The application must restart the serial transmission by writing the SWBStart in
RegSWBSizeH register after writing the next nibble to the RegSWBuff register
SWBempty and TestVar[3] are cleared to "0" at each RegSWBuff register writing operation.
After loading the last nibble in the RegSWBuff register a new interrupt is generated when this data is transferred
to an intermediate Shift Register. Precaution must be made in this case because the SWB will give repetitive
interrupts until the last data is sent out completely and the SWBStart bit goes low automatically. One possibility to
overcome this is to check in the Interrupt subroutine that the SWBStart bit went low before exiting interrupt.
At the end of transmission, one must write RegSWBuff register to set to “0“ TESTvar[3].
SysClk is shown two times longer for a better visibility !
Figure 25 Interactive Serial Write Buffer mode
N.B.
In interactive mode, the number of clocks per package is always equal to 4 and the level of the last bit
of the last package is not latched. These 2 features are valid only in automatic mode.
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