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| 型号： | EVAL-AD7280AEDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 16/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7280 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电池监控器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | SPI 接口 |
| 已供物品： | 板 |
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AD7280A
VIN6
VIN5
VIN4
VIN3
VIN2
ANALOG INPUT STRUCTURE
structure of the AD7280A. The diodes provide ESD protection.
The resistors are lumped components made up of the on
resistance of the input multiplexer, internal track resistance,
and other internal switches. The value of these resistors is
approximately 300 Ω typical. Capacitor C1 is also a lumped
component made up of pin capacitance, ESD diodes, and switch
VIN1
VIN0
ADC V IN+
ADC V IN–
capacitance, whereas Capacitor C2 is the sampling capacitor
of the ADC. The total lumped capacitance of C1 and C2 is
approximately 15 pF.
Figure 23. Mux Configuration During VIN2 to VIN1 Sampling
V DD
The ADC is a successive approximation register analog-to-
digital converter (SAR ADC). The converter is composed of
a comparator, a SAR, control logic, and two capacitive DACs.
V IN+
C1
D
D
R1
C2
the acquisition phase, the SW1, SW2, and SW3 switches are
closed. The sampling capacitor array acquires the signal on the
input during this phase.
V SS
V DD
V REF
CAPACITIVE
DAC
V IN–
D
R1
C2
V IN+
V IN–
B
A SW1
A SW2
C S
COMPARATOR
SW3
CONTROL
LOGIC
C1
V SS
D
B
V REF
C S
CAPACITIVE
DAC
Figure 26. Equivalent Analog Input Circuit
TRANSFER FUNCTION
Figure 24. ADC Configuration During Acquisition Phase
When the ADC starts a conversion, SW3 opens, and SW1 and
SW2 move to Position B, causing the comparator to become
unbalanced (see Figure 25). The control logic and capacitive DACs
are used to add and subtract fixed amounts of charge to return
the comparator to a balanced condition. When the comparator
is rebalanced, the conversion is complete. The control logic gen-
erates the ADC output code. This output code is then stored in
The output coding of the AD7280A is straight binary. The designed
code transitions occur at successive integer LSB values (that is,
1 LSB, 2 LSBs, and so on). The LSB size is dependent on whether
the cell voltage or the auxiliary ADC inputs are being measured.
The analog input range of the voltage inputs is 1 V to 5 V, and
the analog input range of the auxiliary ADC inputs is 0 V to 5 V.
Table 7. LSB Sizes for Each Analog Input Range
the appropriate register for the input that has been converted.
Input
Full-Scale
V IN+
V IN–
V REF
B
A SW1
A SW2
C S
COMPARATOR
SW3
CAPACITIVE
DAC
CONTROL
LOGIC
Selected Inputs
Cell Voltage
Auxiliary ADC Inputs
111...111
Range
1 V to 5 V
0 V to 5 V
Range
4 V/4096
5 V/4096
LSB Size
976 μV
1.22 mV
B
V REF
C S
CAPACITIVE
DAC
111...110
111...000
Figure 25. ADC Configuration During Conversion Phase
011...111
000...010
000...001
000...000
1V + 1LSB
AGND + 1LSB
5V – 1LSB
5V – 1LSB
4V INPUT RANGE
5V INPUT RANGE
ANALOG INPUT
Figure 27. Ideal Transfer Characteristic
Rev. 0 | Page 16 of 48
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| EVAL-AD7298SDZ | 功能描述:BOARD EVAL FOR AD7298 RoHS:是 类别:编程器，开发系统 >> 评估板 - 模数转换器 (ADC) 系列:- 产品培训模块:Obsolescence Mitigation Program 标准包装:1 系列:- ADC 的数量:1 位数:12 采样率（每秒）:94.4k 数据接口:USB 输入范围:±VREF/2 在以下条件下的电源（标准）:- 工作温度:-40°C ~ 85°C 已用 IC / 零件:MAX11645 已供物品:板，软件 |
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