参数资料
型号: EVAL-AD7280AEDZ
厂商: Analog Devices Inc
文件页数: 24/48页
文件大小: 0K
描述: BOARD EVAL FOR AD7280
标准包装: 1
主要目的: 电源管理,电池监控器
嵌入式:
已用 IC / 零件: *
主要属性: *
次要属性: SPI 接口
已供物品:
AD7280A
POWER-DOWN
V DD
The AD7280A provides two power-down options.
0.1μF
10μF
10k ?
?
?
Full power-down (hardware)
Software power-down
V DD MASTER
V REG
1μF
Full Power-Down (Hardware)
The AD7280A can be placed into full power-down mode, which
requires only 5 μA maximum current, by taking the PD pin low.
The falling edge of the PD pin powers down all analog and
digital circuitry.
The AD7280A includes a digital delay filter on the PD pin,
MUST GO TO 0V
IN HARDWARE
POWER-DOWN
DV CC
AV CC
V DRIVE
AD7280A
V REF
C REF
0.1μF
0.1μF
1μF
0.1μF
which protects against a power-down being initiated by noise
or glitches on the hardware PD pin. A hardware power-down
is not initiated until the PD pin is held low for approximately
130 μs. Similarly, the AD7280A is not taken out of power-down
mode until the PD pin is held high for approximately 130 μs.
The digital delay filter does not apply on initial power-up. The
AUX TERM
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
V SS
ALERT
SDO
SDI
SCLK
CS
PD
CNVST
DSP/MICRO-
PROCESSOR
power-on request is accepted by the AD7280A approximately
5 μs after the rising edge of PD.
When placing the AD7280A into full power-down mode, AV CC
and DV CC must fall to 0 V and must not be held high by any
external means. AV CC and DV CC can be held high unintention-
V DD
MUST GO TO 0V IN
HARDWARE POWER-DOWN
Figure 37. V DRIVE Powered from V REG
ally if the auxiliary ADC inputs are greater than the forward
0.1μF
10μF
10k ?
bias on the internal ESD protection diodes. For this reason, it
is recommended that the auxiliary ADC inputs return to 0 V
when the part is placed in full power-down mode.
In addition, all digital inputs on the AD7280A master device
must return to 0 V when the part is placed in full power-down
mode (see Figure 37). However, if an external V DRIVE supply is
used—that is, V DRIVE is not connected to V REG —then only the
V DD MASTER V REG
DV CC
AV CC
AD7280A
V DRIVE
1μF
0.1μF
0.1μF
2.7V TO 5.5V SUPPLY
0.1μF 10μF
CNVST line must return low (see Figure 38 ).
When the AD7280A is placed into full power-down mode, the
device must be left in full power-down for a minimum of 2 ms
when the V REG and V REF pins are decoupled with 1 μF capacitors.
This ensures that the charge on the V REG and V REF decoupling
capacitors dissipates sufficiently to allow the internal power-on
reset circuit to activate when powering the AD7280A back up.
This time is measured from the falling edge of the PD pin.
Figure 18 shows a plot of the voltage on the V REG and V REF pins
as the AD7280A is powering down with 1 μF decoupling
MUST GO TO 0V
IN HARDWARE
POWER-DOWN
AUX TERM
AUX6
AUX5
AUX4
AUX3
AUX2
AUX1
V SS
V REF
C REF
ALERT
SDO
SDI
SCLK
CS
PD
CNVST
1μF
0.1μF
DSP/MICRO-
PROCESSOR
MUST GO TO 0V IN
HARDWARE POWER-DOWN
capacitors on the pins. Figure 20 shows a similar plot but with
10 μF decoupling capacitors on the V REG and V REF pins.
Rev. 0 | Page 24 of 48
Figure 38. V DRIVE Powered from DSP/Microprocessor
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