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参数资料
| 型号： | EVAL-AD7280AEDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 33/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7280 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电池监控器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | SPI 接口 |
| 已供物品： | 板 |
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AD7280A
READING FROM THE AD7280A
There are two types of read operation for the AD7280A:
? Conversion results read
? Register data read
The data returned from a conversion result read operation includes
the device address, the channel address, the write acknowledge
bit, and the 8-bit CRC information, in addition to the 12 bits of
conversion data. Table 21 illustrates the 32-bit read cycle for a
conversion result read.
The data returned from a register data read operation includes
the device address, the register address, the write acknowledge
bit, and the 8-bit CRC information, in addition to the eight bits
of register data. Table 22 illustrates the 32-bit read cycle for a
register data read.
The AD7280A SPI interface, in combination with the daisy-
chain interface, allows the conversion results of any AD7280A
in a stack of eight AD7280As to be read back using an N × 8 ×
32-bit read cycle, where N is defined as the number of conver-
sions completed on that part, that is, 12, 9, or 6 (see Table 8).
Device Address
section. When reading back register or conversion data from
the device using the daisy-chain readback mode, the SDI line
must be set to write to a specific address. That is, the SDI line
should not be allowed to idle high or low, and the address all
parts bit must be set to 0. The address must be either the top
part in the chain of AD7280A devices or an address with a value
higher than that of the top part in the chain. Writing to the
highest available address (Address 0x1F) and setting the address
all parts bit to 0 is recommended. The 32-bit write command is
0xF800030A.
Channel Address
The channel address allows each individual voltage and auxil-
iary ADC input result to be uniquely identified. Each channel
address is four bits wide. The address for each channel is provided
in the register map (see Table 13).
Register Address
The register map for the AD7280A is provided in Table 13. Each
register address is six bits long and is used when writing to or
reading from the on-chip registers of the AD7280A.
Register Data
The register data is the 8-bit register data that was requested in
a previous write command.
Conversion Data
The conversion data is the 12-bit conversion result from the cell
voltage inputs, the auxiliary ADC inputs, or the ADC self-test
conversion.
Write Acknowledge Bit
As described in the Writing to the AD7280A section, an 8-bit
CRC is included in the write command transmitted to the
AD7280A. The CRC is calculated based on Bits[D31:D11]. A
CRC check is completed before the write command is executed
on the device.
Using the same CRC algorithm, the AD7280A calculates the
CRC and compares it to the CRC that was received by the part
in the transmitted write command. If the two CRC values
match, the command is executed and the write acknowledge bit
in the subsequent transmission of data from the device is set. If
the transmitted and calculated CRCs do not match, the write
command is not executed, and the write acknowledge bit is set
to 0. For examples of the use of the write acknowledge bit, see
the Write Acknowledge section.
8-Bit CRC
The AD7280A includes an 8-bit cyclic redundancy check (CRC) on
all data read back from the device. When reading back conversion
data from the AD7280A, the 8-bit CRC includes the device address,
the channel address, the conversion data, and the write acknowl-
edge bit. When reading back register data from the AD7280A,
the 8-bit CRC includes the device address, the register address,
the register data, two reserved zero bits, and the write acknowledge
bit. In both cases, the CRC is generated on Bits[D31:D10] of the
32-bit read cycle and is transmitted using Bits[D9:D2] of the
same read cycle. For more information about the CRC, see the
Table 21. 32-Bit Read Conversion Result Cycle
Device Address 1
D31 to D27
Channel Address
D26 to D23
Conversion Data
D22 to D11
Write Acknowledge
D10
8-Bit CRC
D9 to D2
Reserved (0 Bits)
D1 to D0
1
The device address is configured LSB first. For example, to address the second device in the stack, that is, the first slave device, the sequence of bits input to the
AD7280A should be 10000. The register address, channel address, data bits, and CRC bits are input MSB first.
Table 22. 32-Bit Read Register Data Cycle
Device Address 1
D31 to D27
Register Address
D26 to D21
Register Data
D20 to D13
Reserved (0 Bits)
D12 to D11
Write Acknowledge
D10
8-Bit CRC
D9 to D2
Reserved (0 Bits)
D1 to D0
1
The device address is configured LSB first. For example, to address the second device in the stack, that is, the first slave device, the sequence of bits input to the
AD7280A should be 10000. The register address, data bits, and CRC bits are input MSB first.
Rev. 0 | Page 33 of 48
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