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| 型号： | EVAL-AD7280AEDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 34/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7280 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电池监控器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | SPI 接口 |
| 已供物品： | 板 |
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AD7280A
DAISY-CHAIN INTERFACE
In a battery monitoring application, up to eight AD7280As can
be daisy-chained together to allow up to 48 individual lithium
ion cell voltages to be monitored. Each AD7280A is capable of
monitoring up to six Li-Ion cells and is powered from the top
and bottom voltage of the six Li-Ion cells. As a result, the supply
voltages of each AD7280A are offset by up to 30 V from
adjacent AD7280As in the chain. For this reason, a standard
serial interface daisy-chain method cannot be used.
The AD7280A includes a daisy-chain interface separate from
the standard SPI interface. This daisy-chain interface allows
each AD7280A in the chain to relay data to and from adjacent
AD7280As.
As described in the Serial Interface section, the SPI interface
consists of four signals: CS, SCLK, SDI, and SDO. In addition
to these pins, there are three optional interface pins: ALERT,
CNVST, and PD. Each of these seven interface signals is
mirrored in the daisy-chain interface to allow communication
between adjacent devices in a daisy chain. For example, the
serial clock of each AD7280A is received on the SCLK pin and
passed to the device above it in the daisy chain using the
SCLKhi pin.
The CS, SCLK, SDI, CNVST, and PD pins, which pass data up
the daisy chain, operate as 3 V or 5 V logic interface pins when
the AD7280A is configured as a master device; these pins
ADDRESSING THE AD7280A WHILE READING
BACK CONVERSION OR REGISTER DATA
An SPI interface reads data and writes data at the same time: as
the device is reading in one command, it provides output data
on the SDO pin in the same read/write cycle. When reading both
register and conversion data from the AD7280A using the daisy-
chain readback mode, the SDI line must not idle high or low; it
must be set up to address and write to either the top device used
in the daisy chain or to a device with an address higher than the
top device used in the daisy chain. In either case, the address all
parts bit (Bit D12 in the write command) should be set to 0, and
a valid CRC must be included. Writing to the highest available
address, that is, Address 0x1F, and setting the address all parts
bit to 0 is recommended. The 32-bit write command is
0xF800030A.
INITIALIZING THE AD7280A
On initial power-up and when coming out of power-down, all
AD7280As default to a device address of 0x00. The following
sequence of commands should be followed to allow each AD7280A
in the daisy chain to recognize its unique position in the chain.
The following sequence allows device addresses on all parts in
the chain to be configured and confirmed through daisy-chain
readback. A subset of these commands can also be used to
configure the device addresses without readback confirmation.
operate as daisy-chain interface pins when the AD7280A is
configured as a slave device.
The SDO and ALERT pins operate as 3 V or 5 V logic interface
pins when the AD7280A is configured as a master device. These
pins are tristated when the AD7280A is configured as a slave
device. Two additional pins, SDOlo and ALERTlo, are required
to pass data down the daisy chain.
As described in the Serial Interface section, only one 32-bit
write cycle is required to write to any register in a stack of eight
AD7280As. The readback of conversion data from all channels
monitoring the battery stack requires an N × 8 × 32-bit read cycle,
where N is defined as the number of conversions completed on
that part, that is, 12, 9, or 6. The recommended SCLK frequency
to ensure correct operation of the daisy-chain interface is 1 MHz.
With a 1 MHz SCLK, it takes approximately 1.54 ms to read
back the voltage conversions on 48 channels.
When reading from a single device in a stack of AD7280A devices
(daisy-chain register readback is disabled; Bit D0 of the control
register = 0), the SCLK frequency must be lower than 1 MHz to
read back the register data from parts up the chain of AD7280As.
1.
2.
3.
4.
A single command should be sent to all devices in the
chain to assert the lock device address bit (D2), to deassert
the increment device address bit (D1), and to assert the
daisy-chain register readback bit (D0). The 32-bit write
command is 0x01C2B6E2.
A second command should be sent to all devices in the
chain to write the address of the lower byte of the control
register, 0x0E, to the read register on all devices. The 32-bit
write command is 0x038716CA.
To verify that all AD7280As in the chain have received and
locked their unique device address, a daisy-chain register read
should be requested from all devices. This can be done by
continuing to apply sets of 32 SCLKs framed by CS until
the lower byte of the control register of each device in the
daisy chain has been read back. The user should confirm
that all device addresses are in sequence. The 32-bit write
command is 0xF800030A.
This command should be repeated until the control
register data has been read back from all devices in the
daisy chain.
This is due to the propagation delay between adjacent parts in
the daisy chain (see t DELAY in Table 3). This delay does not apply
if the part is reading registers or conversion data from the part
in daisy-chain mode; that is, the maximum SCLK of 1 MHz can
always be used in daisy-chain mode.
Rev. 0 | Page 34 of 48
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