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| 型号： | EVAL-AD7280AEDZ |
| 厂商： | Analog Devices Inc |
| 文件页数： | 4/48页 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL FOR AD7280 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电池监控器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | * |
| 主要属性： | * |
| 次要属性： | SPI 接口 |
| 已供物品： | 板 |
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AD7280A
Parameter
Min
Typ
Max
Unit
Test Conditions/Comments
REGULATOR OUTPUT (V REG )
Input Voltage Range
8
30
V
4.9
5.2
5.5
V
5 mA external load
Output Current 14
Line Regulation
Load Regulation
0.5
2.5
5
mA
mV/V
mV/mA
Internal Short Protection Limit
25
mA
For a 10 Ω short
CELL BALANCING OUTPUTS 15
Output High Voltage, V OH
V REG ? 1
5
V REG + 0.2
V
I SOURCE = 415 nA
Output Low Voltage, V OL
0
V
CB1 Output Ramp-Up Time 16
CB1 Output Ramp-Down Time 17
CB2 to CB6 Output Ramp-Up Time 16
30
30
380
30
μs
μs
μs
μs
For an 80 pF load
For an 80 pF load
For an 80 pF load
For an 80 pF load
LOGIC INPUTS
Input High Voltage, V INH
Input Low Voltage, V INL
Input Current, I IN
Input Capacitance, C IN
LOGIC OUTPUTS
2.4
5
0.4
±10
V
V
μA
pF
Output High Voltage, V OH
Output Low Voltage, V OL
Floating State Leakage Current
Floating State Output Capacitance
Output Coding
V DRIVE × 0.9
5
Straight binary
0.4
±10
V
V
μA
pF
I SOURCE = 200 μA
I SINK = 200 μA
1
2
3
4
5
6
7
8
9
For dc accuracy specifications, the LSB size for cell voltage measurements is (2 × V REF ? 1 V)/4096. The LSB size for auxiliary ADC input voltage measurements is (2 × V REF )/4096.
ADC unadjusted error includes the INL of the ADC and the gain and offset errors of the VIN0 to VIN6 input channels.
The conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. The ADC unadjusted error increases by a factor of 4.
Total unadjusted error includes the INL of the ADC and the gain and offset errors of the VIN0 to VIN6 input channels, as well as the reference error, that is, the difference between
the ideal and actual reference voltage and the temperature coefficient of the 2.5 V reference.
The conversion accuracy during cell balancing is decreased due to the activation of the cell balance circuitry. The total unadjusted error increases by a factor of 4.
For the full analog input range, that is, 1 V to 2 × V REF , the total unadjusted error increases by 20%.
The total current measured on the input pins while converting is the sum of the static and dynamic leakage currents. See the Terminology section.
Bit D3 of the control register is set to 0 (thermistor termination resistor function is not in use).
ADC unadjusted error includes the INL of the ADC and the gain and offset errors of the AUXx input channels.
10
Total unadjusted error includes the INL of the ADC and the gain and offset errors of the AUXx input channels, as well as the reference error, that is, the difference between the
ideal and actual reference voltage and the temperature coefficient of the 2.5 V reference.
11
The turn-on settling time is the time from the rising edge of the PD signal until the conversion result settles to the specified accuracy. This includes the time required
to power up the regulator and the reference. Note that a rising edge on the CNVST input is also required to power up the reference. This rising edge should occur after
the rising edge on PD.
12
13
14
15
16
Sample tested during initial release to ensure compliance.
The regulator output voltage is specified with an external 5 mA load in addition to the current required to drive the AV CC , DV CC , and V DRIVE supplies of the AD7280A.
This specification refers to the maximum regulator output current that is available for external use.
The CBx outputs can be set to 0 V or V REG with respect to the negative terminal of the cell being balanced.
The CB1 to CB6 output ramp-up times are defined from the rising edge of the CS command until the CB output exceeds V REG ? 1 V with respect to the negative
terminal of the cell being balanced.
17
The CB1 to CB6 output ramp-down times are defined from the rising edge of the CS command until the CB output falls below 50 mV with respect to the negative
terminal of the cell being balanced.
Rev. 0 | Page 4 of 48
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