参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 10/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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ADE7763
Data Sheet
Pin No.
14
15
16
17
18
19
20
Mnemonic
IRQ
CLKIN
CLKOUT
CS
SCLK
DOUT
DIN
Description
Interrupt Request Output. This is an active low, open-drain logic output. Maskable interrupts include active
energy register rollover, active energy register at half level, and arrivals of new waveform samples—see the
Interrupts section.
Master Clock for ADCs and Digital Signal Processing. An external clock can be provided at this logic input.
Alternatively, a parallel resonant AT crystal can be connected across CLKIN and CLKOUT to provide a clock
source for the ADE7763. The clock frequency for specified operation is 3.579545 MHz. Ceramic load
capacitors between 22 pF and 33 pF should be used with the gate oscillator circuit. Refer to the crystal
manufacturer’s data sheet for load capacitance requirements.
A crystal can be connected across this pin and CLKIN, as described for Pin 15, to provide a clock source for
the ADE7763. The CLKOUT pin can drive one CMOS load when either an external clock is supplied at CLKIN
or a crystal is being used.
Chip Select 1 . Part of the 4-wire SPI serial interface. This active low logic input allows the ADE7763 to share
the serial bus with several other devices—see the Serial Interface section.
Serial Clock Input for the Synchronous Serial Interface 1 . All serial data transfers are synchronized to this
clock—see the Serial Interface section. The SCLK has a Schmitt-trigger input for use with a clock source
that has a slow edge transition time, such as an opto-isolator output.
Data Output for the Serial Interface. Data is shifted out at this pin upon the rising edge of SCLK. This logic
output is normally in a high impedance state, unless it is driving data onto the serial data bus—see the
Data Input for the Serial Interface. Data is shifted in at this pin upon the falling edge of SCLK—see the
1
It is recommended to drive the RESET, SCLK, and CS pins with either a push-pull without an external series resistor or with an open-collector with a 10 k? pull-up Pull-
down resistors are not recommended because under some conditions, they may interact with internal circuitry.
Rev. C | Page 10 of 56
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