参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 53/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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Data Sheet
ADE7763
INTERRUPT STATUS REGISTER (0x0B),
RESET INTERRUPT STATUS REGISTER (0x0C),
INTERRUPT ENABLE REGISTER (0x0A)
The status register is used by the MCU to determine the source of an interrupt request (IRQ). When an interrupt event occurs, the
corresponding flag in the interrupt status register is set to logic high. If the enable bit for this flag is Logic 1 in the interrupt enable register,
the IRQ logic output will go active low. When the MCU services the interrupt, it must first carry out a read from the interrupt status
register to determine the source of the interrupt.
Table 12.
Bit
Interrupt
Location
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
Flag
AEHF
SAG
CYCEND
WSMP
ZX
TEMP
RESET
AEOF
PKV
PKI
VAEHF
VAEOF
ZXTO
PPOS
PNEG
RESERVED
Description
Indicates that an interrupt occurred because the active energy register, AENERGY, is more than half full.
Indicates that an interrupt was caused by a sag on the line voltage.
Indicates the end of energy accumulation over an integral number of half line cycles, as defined by the content
of the LINECYC register—see the Line Cycle Energy Accumulation Mode section.
Indicates that new data is present in the waveform register.
This status bit is set to 1 on the rising and falling edge of the voltage waveform, see the Zero-Crossing
Detection section.
Indicates that a temperature conversion result is available in the temperature register.
Indicates the end of a reset for software and hardware resets. The corresponding enable bit has no function in
the interrupt enable register, i.e., this status bit is set at the end of a reset, but cannot be enabled to cause an
interrupt.
Indicates that the active energy register has overflowed.
Indicates that the waveform sample from Channel 2 has exceeded the VPKLVL value.
Indicates that the waveform sample from Channel 1 has exceeded the IPKLVL value.
Indicates that an interrupt occurred because the apparent energy register, VAENERGY, is more than half full.
Indicates that the apparent energy register has overflowed.
Indicates that an interrupt was caused by a missing zero crossing on the line voltage for a specified number of
line cycles—see the Zero-Crossing Timeout section.
Indicates that the power has gone from negative to positive.
Indicates that the power has gone from positive to negative.
Reserved.
15 14 13 12 11 10
9
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
ADDR: 0x0A, 0x0B, 0x0C
RESERVED
PNEG
(POWER POSITIVE TO NEGATIVE)
PPOS
(POWER NEGATIVE TO POSITIVE)
ZXTO
(ZERO-CROSSING TIMEOUT)
VAEOF
(VAENERGY OVERFLOW)
VAEHF
(VAENERGY IS HALF FULL)
PKI
(CHANNEL 1 SAMPLE ABOVE IPKLVL)
PKV
(CHANNEL 2 SAMPLE ABOVE VPKLVL)
Figure 87. Interrupt Status/Interrupt Enable Register
Rev. C | Page 53 of 56
AEHF
(ACTIVE ENERGY HALF FULL)
SAG
(SAG ONLINE VOLTAGE)
CYCEND
(END OF LINECYC HALF LINE CYCLES)
WSMP
(WAVEFORM SAMPLES DATA READY)
ZX
(ZERO CROSSING)
TEMP
(TEMPERATURE DATA READY)
RESET
(END OF SOFTWARE/HARDWARE RESET)
AEOF
(ACTIVE ENERGY REGISTER OVERFLOW)
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