参数资料
| 型号： | EVAL-ADE7763ZEB |
| 厂商： | Analog Devices Inc |
| 文件页数： | 51/56页 |
| 文件大小： | 0K |
| 描述： | BOARD EVALUATION FOR ADE7763 |
| 标准包装： | 1 |
| 主要目的： | 电源管理，电度表/功率表 |
| 已用 IC / 零件： | ADE7763 |
| 已供物品： | 板 |
| 相关产品： | ADE7763ARSZRLDKR-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLCT-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZ-ND - IC ENERGY METERING 1PHASE 20SSOP ADE7763ARSZRLTR-ND - IC ENERGY METERING 1PHASE 20SSOP |
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Data Sheet
ADE7763
REGISTER DESCRIPTIONS
All ADE7763 functionality is accessed via on-chip registers. Each register is accessed by first writing to the communication register and
then transferring the register data. A full description of the serial interface protocol is given in the Serial Interface section.
COMMUNICATION REGISTER
The communication register is an 8-bit, write-only register that controls the serial data transfer between the ADE7763 and the host
processor. All data transfer operations must begin with a write to the communication register. The data written to the communication
register determines whether the next operation is a read or a write and which register is being accessed. Table 10 outlines the bit
designations for the communication register.
DB7
W/R
DB6
0
DB5
A5
DB4
A4
DB3
A3
DB2
A2
DB1
A1
DB0
A0
Table 10. Communication Register
Bit
Bit
Location
0 to 5
6
7
Mnemonic
A0 to A5
RESERVED
W/R
Description
The 6 LSBs of the communication register specify the register for the data transfer operation. Table 9 lists the
address of each on-chip register.
This bit is unused and should be set to 0.
When this bit is a Logic 1, the data transfer operation immediately following the write to the communication
register is interpreted as a write to the ADE7763. When this bit is a Logic 0, the data transfer operation
immediately following the write to the communication register is interpreted as a read operation.
MODE REGISTER (0x09)
The ADE7763 functionality is configured by writing to the mode register. Table 11 describes the functionality of each bit
in the register.
Table 11.
Bit
Bit
Default
Location
0
1
2
3
4
Mnemonic
DISHPF
DISLPF2
DISCF
DISSAG
ASUSPEND
Value
0
0
1
1
0
Description
HPF (high-pass filter) in Channel 1 is disabled when this bit is set.
LPF (low-pass filter) after the multiplier (LPF2) is disabled when this bit is set.
Frequency output CF is disabled when this bit is set.
Line voltage sag detection is disabled when this bit is set.
By setting this bit to Logic 1, both A/D converters can be turned off. During normal operation, this
bit should be left at Logic 0. All digital functionality can be stopped by suspending the clock
signal at CLKIN pin.
5
TEMPSEL
0
Temperature conversion starts when this bit is set to 1. This bit is automatically reset to 0 after the
temperature conversion.
6
SWRST
0
Software Chip Reset. A data transfer should not take place to the ADE7763 for at least 18 μs after a
software reset.
7
8
9
10
CYCMODE
DISCH1
DISCH2
SWAP
0
0
0
0
Setting this bit to Logic 1 places the chip in line cycle energy accumulation mode.
ADC 1 (Channel 1) inputs are internally shorted together.
ADC 2 (Channel 2) inputs are internally shorted together.
By setting this bit to Logic 1, the analog inputs V2P and V2N are connected to ADC 1 and the
analog inputs V1P and V1N are connected to ADC 2.
12, 11
DTRT1, 0
00
Use these bits to select the waveform register update rate.
DTRT1
DTRT0
Update Rate
0
0
27.9 kSPS (CLKIN/128)
0
1
14 kSPS (CLKIN/256)
1
0
7 kSPS (CLKIN/512)
1
1
3.5 kSPS (CLKIN/1024)
Rev. C | Page 51 of 56
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